Texas Instruments TMS320DM646x User Manual page 28

Architecture
Example 2. Receive Buffer Descriptor in C Structure Format
/*
// EMAC Descriptor
//
// The following is the format of a single buffer descriptor
// on the EMAC.
*/
typedef struct _EMAC_Desc {
struct _EMAC_Desc *pNext;
Uint8
Uint32
*/
Uint32
} EMAC_Desc;
/* Packet Flags
#define EMAC_DSC_FLAG_SOP
#define EMAC_DSC_FLAG_EOP
#define EMAC_DSC_FLAG_OWNER
#define EMAC_DSC_FLAG_EOQ
#define EMAC_DSC_FLAG_TDOWNCMPLT
#define EMAC_DSC_FLAG_PASSCRC
#define EMAC_DSC_FLAG_JABBER
#define EMAC_DSC_FLAG_OVERSIZE
#define EMAC_DSC_FLAG_FRAGMENT
#define EMAC_DSC_FLAG_UNDERSIZED
#define EMAC_DSC_FLAG_CONTROL
#define EMAC_DSC_FLAG_OVERRUN
#define EMAC_DSC_FLAG_CODEERROR
#define EMAC_DSC_FLAG_ALIGNERROR
#define EMAC_DSC_FLAG_CRCERROR
#define EMAC_DSC_FLAG_NOMATCH
2.5.5.3 Buffer Offset
This 16-bit field must be initialized to zero by the software application before adding the descriptor to a
receive queue.
Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register. When the
offset register is set to a non-zero value, the received packet is written to the packet buffer at an offset
given by the value of the register, and this value is also written to the buffer offset field of the descriptor.
When a packet is fragmented over multiple buffers because it does not fit in the first buffer supplied, the
buffer offset only applies to the first buffer in the list, which is where the start of packet (SOP) flag is set in
the corresponding buffer descriptor. In other words, the buffer offset field is only updated by the EMAC on
SOP descriptors.
The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest
value of buffer length for all descriptors in the list.
28 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
/* Pointer to next descriptor in chain
*pBuffer; /* Pointer to data buffer
BufOffLen; /* Buffer Offset(MSW) and Length(LSW)
PktFlgLen; /* Packet Flags(MSW) and Length(LSW)
0x80000000u
0x40000000u
0x20000000u
0x10000000u
0x08000000u
0x04000000u
0x02000000u
0x01000000u
0x00800000u
0x00400000u
0x00200000u
0x00100000u
0x00080000u
0x00040000u
0x00020000u
0x00010000u
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*/
*/
*/
*/
SPRUEQ6 – December 2007
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