Phy Acknowledge Status Register (Alive); Phy Link Status Register (Link); Phy Acknowledge Status Register (Alive) Field Descriptions; Phy Link Status Register (Link) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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4.3

PHY Acknowledge Status Register (ALIVE)

The PHY acknowledge status register (ALIVE) is shown in
31
15
LEGEND: R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 27. PHY Acknowledge Status Register (ALIVE) Field Descriptions
Bit Field Value
31-0 ALIVE 0-FFFF FFFFh
0
1
4.4

PHY Link Status Register (LINK)

The PHY link status register (LINK) is shown in
31
15
LEGEND: R = Read only; -n = value after reset
Bit Field Value
31-0 LINK 0-FFFF FFFFh
0
1
SPRUEQ6 – December 2007
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Figure 29. PHY Acknowledge Status Register (ALIVE)
Description
MDIO Alive bits. Each of the 32 bits of this register is set if the most recent access to the PHY with
address corresponding to the register bit number was acknowledged by the PHY; the bit is reset if
the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause
the corresponding alive bit to be updated. The alive bits are only meant to be used to give an
indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit
will clear it, writing a 0 has no effect.
The PHY fails to acknowledge the access.
The most recent access to the PHY with an address corresponding to the register bit number was
acknowledged by the PHY.
Figure 30. PHY Link Status Register (LINK)
Table 28. PHY Link Status Register (LINK) Field Descriptions
Description
MDIO Link state bits. This register is updated after a read of the generic status register of a PHY.
The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the
read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge
the read transaction. Writes to the register have no effect.
The PHY indicates it does not have a link or fails to acknowledge the read transaction
The PHY with the corresponding address has a link and the PHY acknowledges the read
transaction.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 29 and described in
ALIVE
R/W1C-0
ALIVE
R/W1C-0
Figure 30 and described in
LINK
R-0
LINK
R-0
MDIO Registers
Table 27.
Table 28.
16
0
16
0
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