Texas Instruments TMS320DM646X DMSOC User Manual
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Texas Instruments TMS320DM646X DMSOC User Manual

Dmsoc asynchronous external memory interface (emif)
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TMS320DM646x DMSoC
Asynchronous External Memory Interface
(EMIF)
User's Guide
Literature Number: SPRUEQ7C
February 2010

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  • Page 1 TMS320DM646x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide Literature Number: SPRUEQ7C February 2010...
  • Page 2 SPRUEQ7C – February 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    EMIF Interrupt Mask Clear Register (EIMCR) NAND Flash Control Register (NANDFCR) NAND Flash Status Register (NANDFSR) 4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) Appendix A Revision History SPRUEQ7C – February 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Table of Contents...
  • Page 4 EMIF Interrupt Mask Clear Register (EIMCR) NAND Flash Control Register (NANDFCR) NAND Flash Status Register (NANDFSR) NAND Flash n ECC Register (NANDECCn) List of Figures List of Figures Copyright © 2010, Texas Instruments Incorporated www.ti.com SPRUEQ7C – February 2010 Submit Documentation Feedback...
  • Page 5 NAND Flash Control Register (NANDFCR) Field Descriptions NAND Flash Status Register (NANDFSR) Field Descriptions NAND Flash n ECC Register (NANDECCn) Field Descriptions Document Revision History SPRUEQ7C – February 2010 Submit Documentation Feedback List of Tables Copyright © 2010, Texas Instruments Incorporated List of Tables...

  • Page 6: Preface

    The current documentation that describes the DM646x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000. SPRUEP8 — TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signal processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). SPRUEP9 —...
  • Page 7 (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRUEQ7C – February 2010 Submit Documentation Feedback Related Documentation From Texas Instruments Copyright © 2010, Texas Instruments Incorporated Read This First...

  • Page 8: Introduction

    Asynchronous devices including Flash and SRAM • Host processor interfaces such as the host port interface (HPI) on a Texas Instruments Digital Signal Processor (DSP) The most common use for the EMIF is to interface with both flash devices and SRAM devices. The Example Configuration section contains examples of operating the EMIF in this configuration.

  • Page 9: Functional Block Diagram

    4. Changes to the frequency of the input clock to PLL controller 0 and to the PLL controller 0 multiplier values alters the operating frequency of the EMIF. See the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9) for more information on how to program the PLL controller.

  • Page 10: Signal Descriptions

    Table 1. EMIF Pins Select Strobe Mode Operation of EM_CS[5:2] Active during the entire asynchronous access cycle Active only during the strobe period of an access cycle Copyright © 2010, Texas Instruments Incorporated www.ti.com Section 2.5.8. To enable SPRUEQ7C – February 2010...

  • Page 11: Emif Asynchronous Interface

    A[1:0] a) EMIF to 8-bit memory interface asynchronous DQ[15:0] A[22:1] EM_BA[1] A[0] b) EMIF to 16-bit memory interface Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture show the mapping between the EMIF 8−bit memory 16−bit memory...

  • Page 12: Description Of The Asynchronous Configuration Register (Acfgn)

    Refer to the datasheet of the external asynchronous device to determine the appropriate setting for this field. Asynchronous External Memory Interface (EMIF) Section 2.5.8 for more details on this mode of operation. Copyright © 2010, Texas Instruments Incorporated www.ti.com SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 13: Description Of The Asynchronous Wait Cycle Configuration Register (Awccr)

    2.5.1. This field also determines the number of external accesses required to fulfill a request Section Section 2.5.11 Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture 2.2. For example, a request for a 32-bit word for more information about the EMIF...

  • Page 14: Asynchronous Read Operation In Normal Mode

    If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated www.ti.com Section 2.2...

  • Page 15: Timing Waveform Of An Asynchronous Read Cycle In Normal Mode

    Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold Internal clock EM_CS[5:2] EM_A/EM_BA Address EM_D Data EM_OE EM_WE EM_RW SPRUEQ7C – February 2010 Asynchronous External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated...

  • Page 16: Asynchronous Write Operation In Normal Mode

    If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. Asynchronous External Memory Interface (EMIF) Figure Copyright © 2010, Texas Instruments Incorporated www.ti.com Section 2.2 request a write...

  • Page 17: Timing Waveform Of An Asynchronous Write Cycle In Normal Mode

    Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Internal clock EM_CS[5:2] EM_A/EM_BA EM_D EM_OE EM_WE EM_RW SPRUEQ7C – February 2010 Submit Documentation Feedback Strobe Setup Address Data Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture Hold...

  • Page 18: Asynchronous Read Operation In Select Strobe Mode

    If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated www.ti.com Section 2.2...

  • Page 19: Timing Waveform Of An Asynchronous Read Cycle In Select Strobe Mode

    Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Internal clock EM_CS[5:2] EM_A/EM_BA EM_D EM_OE EM_WE EM_RW SPRUEQ7C – February 2010 Submit Documentation Feedback Strobe Setup Address Data Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture Hold...

  • Page 20: Asynchronous Write Operation In Select Strobe Mode

    If this is the case, the EMIF instead enters directly into the turn-around period for the pending read or write operation. Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated www.ti.com Section 2.2...

  • Page 21: Timing Waveform Of An Asynchronous Write Cycle In Select Strobe Mode

    Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode Internal clock EM_CS[5:2] EM_A/EM_BA EM_D EM_OE EM_WE EM_RW SPRUEQ7C – February 2010 Submit Documentation Feedback Strobe Setup Address Data Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture Hold...

  • Page 22: Description Of The Nand Flash Control Register (Nandfcr)

    Configuration Value Section 3.2 Section 3.2 Section 3.2 Programmed to equal the width of the NAND Flash device Copyright © 2010, Texas Instruments Incorporated www.ti.com Table 12 lists the bit fields that must for information on how to program. for information on how to program.

  • Page 23: Emif To Nand Flash Interface

    EM_WE EM_OE EM_D[7:0] IO[7:0] EM_WAIT[n] a) Connection to 8-bit NAND device EMIF NAND flash CLE_EM_A[16] ALE_EM_A[17] EM_CS[n] EM_WE EM_OE EM_D[15:0] IO[15:0] EM_WAIT[n] b) Connection to 16-bit NAND device Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture...
  • Page 24 • AB synchronized Asynchronous External Memory Interface (EMIF) time for a read. See Section 2.5.6.8 for workaround. Copyright © 2010, Texas Instruments Incorporated www.ti.com time for a read. See Section 2.5.6.8 Section 2.5.6.5 SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 25: Ecc Value For 8-Bit Nand Flash

    Bit 3 Bit 2 Bit 1 Bit 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture Figure 9 p16e p32e p2048e p16o p16e p2048o p32o p16o...

  • Page 26: Emif To 16-Bit Multiplexed Hpi16 Interface

    HD[15:0] EM_RW HR/W EM_A[1:0] HCNTL[1:0] EM_WAIT HRDY EM_OE HDS1 EM_WE HDS2 EM_CS EM_BA1 HHWIL GPIOx HINT HPIENA HBED HBE1 Copyright © 2010, Texas Instruments Incorporated www.ti.com Section 2.5.11.1 Figure 10 shows the connection SPRUEQ7C – February 2010 Submit Documentation Feedback...
  • Page 27 Following device power up and deassertion of the RESET pin, the internal clock to the EMIF is turned on and the EMIF memory-mapped registers are programmed to their default values. SPRUEQ7C – February 2010 Submit Documentation Feedback for details on enabling this interrupt. Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Architecture...

  • Page 28: Emif Interrupt

    Architecture 2.5.11 Interrupt Support The EMIF has a single interrupt source information on the ARM interrupt controller (AINTC), see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). ARM Event The EMIF supports a single interrupt to the CPU. masking of EMIF interrupts and 2.5.11.1...
  • Page 29 EMIF through the use of the Power and Sleep Controller (PSC). When the PSC sends a clock stop request to the EMIF, the EMIF will complete pending transfers before issuing a clock stop acknowledge, allowing the PSC to stop the clock. See the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9) for more information.

  • Page 30: Use Cases

    Figure 11. Connecting the EMIF to the TC55V16100FT-12 Asynchronous External Memory Interface (EMIF) for more information. EMIF TC5516100FT−12 EM_CS EM_WE EM_OE A[18:0] A[19:1] EM_BA[1] A[0] EM_D[15:0] DQ[15:0] Copyright © 2010, Texas Instruments Incorporated www.ti.com SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 31: Emif Input Timing Requirements

    AC timing specifications that must be considered. is the period at which the EMIF operates. The (m) ) t R_HOLD w TA w Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases in the Figure 12, the equation for TA can be...

  • Page 32: Timing Waveform Of An Asram Read

    Write Recovery time Data Hold time Write Cycle time Asynchronous External Memory Interface (EMIF) Setup Strobe lists the AC timing specifications that must be satisfied. Copyright © 2010, Texas Instruments Incorporated www.ti.com Hold SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 33: Timing Waveform Of An Asram Write

    EM_D[15:0] SPRUEQ7C – February 2010 Submit Documentation Feedback is the period at which the EMIF operates. The W_STROBE w W_HOLD w max Setup Strobe Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases in the Hold...

  • Page 34: Asram Timing Requirements With Pcb Delays

    EMIF operates. The (m) ) t EM_A (m) * t EM_D EM_A (m) ) t EM_D EM_CS TA w Copyright © 2010, Texas Instruments Incorporated www.ti.com due to PCB affects. The PCB in the EM_D SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 35: Timing Waveform Of An Asram Read With Pcb Delays

    W_SETUP width in EMIF clock cycles minus 1 cycle. SPRUEQ7C – February 2010 Submit Documentation Feedback Setup Strobe EM_OE EM_OE EM_D is the period at which the EMIF operates. The Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases Hold EM_A EM_D in the...

  • Page 36: Timing Waveform Of An Asram Write With Pcb Delays

    W_STROBE w (m) * t EM_A EM_WE (m) * t EM_WE EM_A EM_WE Setup Strobe EM_WE EM_D Copyright © 2010, Texas Instruments Incorporated www.ti.com (m) * t EM_D EM_WE (m) * t EM_D Hold EM_CS EM_A EM_WE EM_D SPRUEQ7C – February 2010...

  • Page 37: Emif Timing Requirements For Tc5516100Ft-12 Example

    SPRUEQ7C – February 2010 Submit Documentation Feedback = 10 nS) Table 21 Read Access Write Access Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases lists the data sheet specifications Units Units Delay (ns) 0.36 0.27 0.36...
  • Page 38 EM_WE ( 0.27 ) 9 * 0.36 ) ( 0.45 ) 7 * 0.36 ) * 3 w Copyright © 2010, Texas Instruments Incorporated www.ti.com ( 0.27 ) 12 ) 5 ) 0.45 ) * 1 w 0.78 * 3 w * 1.8 * 1 w * 1.37...

  • Page 39: Interfacing To Nand Flash

    • TA = 0 Asynchronous Device Bus Width. • ASIZE = 1, select a 16-bit data bus width Section 3.1. Table 24. Recommended Margins Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases Table 23. In this...

  • Page 40: Emif Read Timing Requirements

    R_SETUP, R_STROBE, and R_HOLD. Asynchronous External Memory Interface (EMIF) list the AC timing parameters that must be considered. Copyright © 2010, Texas Instruments Incorporated www.ti.com SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 41: Timing Waveform Of A Nand Flash Read

    R_SETUP w (m) ) t (m) ) t R_HOLD w Figure (m) * (R_HOLD ) 1)t Setup Strobe Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases in the 16, the equation for TA can be Hold...

  • Page 42: Nand Flash Write Timing Requirements

    W_HOLD w max W_SETUP ) W_STROBE ) W_HOLD w Asynchronous External Memory Interface (EMIF) W_STROBE w W_SETUP ) W_STROBE w Copyright © 2010, Texas Instruments Incorporated www.ti.com is the period at which the EMIF SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 43: Timing Waveform Of A Nand Flash Command Write

    Figure 18. Timing Waveform of a NAND Flash Address Write EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] SPRUEQ7C – February 2010 Submit Documentation Feedback Setup Strobe Setup Strobe Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases Hold Hold...

  • Page 44: Timing Waveform Of A Nand Flash Data Write

    Use Cases Figure 19. Timing Waveform of a NAND Flash Data Write EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] Asynchronous External Memory Interface (EMIF) Setup Strobe Copyright © 2010, Texas Instruments Incorporated www.ti.com Hold SPRUEQ7C – February 2010 Submit Documentation Feedback...

  • Page 45: Emif Timing Requirements For Hy27Ua081G1M Example

    CS Hold time Data Hold time Write Cycle time SPRUEQ7C – February 2010 Submit Documentation Feedback = 10 nS) Table 29 Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases lists the data sheet specifications Units Units...
  • Page 46 * 1 w 60 * 1 w 5 * 1 w * 1 w 20 * 3 w 80 Copyright © 2010, Texas Instruments Incorporated www.ti.com * 1 w 5.5 (75 ) 5) * 1 w 7 * 1 w * 3...

  • Page 47: Configuring A1Cr For Hy27Ua081G1M Example

    Minimum turnaround time. • TA = 2 Asynchronous device bus width. • ASIZE = 0, select an 8-bit data bus width. Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Use Cases Table 30. In this Table 31. In NANDFCR,...

  • Page 48: Registers

    NAND Flash Status Register NAND Flash 1 ECC Register (CS2 Space) NAND Flash 2 ECC Register (CS3 Space) NAND Flash 3 ECC Register (CS4 Space) NAND Flash 4 ECC Register (CS5 Space) Copyright © 2010, Texas Instruments Incorporated www.ti.com Table 32 should Section Section 4.1...

  • Page 49: Revision Code And Status Register (Rcsr)

    Minor Revision. EMIF code revisions are indicated by a revision code taking the format REVMAJ.REVMIN. Current minor revision. SPRUEQ7C – February 2010 Submit Documentation Feedback Figure 20 MODID R-Fh Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers and described in Table REVMIN R-2h...

  • Page 50: Asynchronous Wait Cycle Configuration Register (Awccr)

    EM_WAIT[3] pin is used. EM_WAIT[4] pin is used. EM_WAIT[5] pin is used. Asynchronous External Memory Interface (EMIF) Figure 21 Reserved CS5_WAIT CS4_WAIT R/W-3h Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table CS3_WAIT CS2_WAIT R/W-2h R/W-1 R/W-0 MEWC R/W-80h SPRUEQ7C –...
  • Page 51 Maximum extended wait cycles. The EMIF will wait for a maximum of (MEWC + 1) × 16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access. SPRUEQ7C – February 2010 Submit Documentation Feedback Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers...

  • Page 52: Asynchronous N Configuration Registers (A1Cr-A4Cr)

    35. There are four ACFGns. Each chip select space has a W_SETUP R/W-Fh R_STROBE R_HOLD R/W-3Fh R/W-7h Section 2.5 for details on the two modes of operation. for details. Copyright © 2010, Texas Instruments Incorporated www.ti.com W_STROBE R/W-3Fh W_HOLD R_SETUP R/W-7h R/W-Fh ASIZE R/W-3h R/W-0 Section 2.5.8...

  • Page 53: Emif Interrupt Raw Register (Eirr)

    EMIF interrupt mask register (EIMR). SPRUEQ7C – February 2010 Submit Documentation Feedback Table Figure 23. EMIF Interrupt Raw Register (EIRR) Reserved Reserved R/W1C-0 R/W1C-0 Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers Reserved R/W1C-0 R/W1C-0...

  • Page 54: Emif Interrupt Mask Register (Eimr)

    Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. Asynchronous External Memory Interface (EMIF) Figure 24 Reserved Reserved WRM2 WRM1 R/W1C-0 R/W1C-0 R/W1C-0 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table WRM0 Reserved R/W1C-0 SPRUEQ7C – February 2010 Submit Documentation Feedback...
  • Page 55 Indicates that an asynchronous timeout interrupt has been generated. Writing a 1 will clear this bit and the AT bit in the EMIF interrupt raw register (EIRR). SPRUEQ7C – February 2010 Submit Documentation Feedback Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers...

  • Page 56: Emif Interrupt Mask Set Register (Eimsr)

    Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. Asynchronous External Memory Interface (EMIF) Reserved Reserved WRMSET2 WRMSET1 WRMSET0 R/W1S-0 R/W1S-0 R/W1S-0 Copyright © 2010, Texas Instruments Incorporated www.ti.com Figure 25 Reserved ATMSET R/W1S-0 SPRUEQ7C – February 2010 Submit Documentation Feedback...
  • Page 57 Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect. Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 sets this bit and the ATMCLR bit in EIMCR. SPRUEQ7C – February 2010 Submit Documentation Feedback Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers...

  • Page 58: Emif Interrupt Mask Clear Register (Eimcr)

    Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. Asynchronous External Memory Interface (EMIF) Reserved Reserved WRMCLR2 WRMCLR1 WRMCLR0 R/W1C-0 R/W1C-0 R/W1C-0 Copyright © 2010, Texas Instruments Incorporated www.ti.com Figure 26 Reserved ATMCLR R/W1C-0 SPRUEQ7C – February 2010 Submit Documentation Feedback...
  • Page 59 Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect. Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 clears this bit and the ATMSET bit in EIMSR. SPRUEQ7C – February 2010 Submit Documentation Feedback Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers...

  • Page 60: Nand Flash Control Register (Nandfcr)

    Not using NAND Flash. Using NAND Flash on EM_CS2. Asynchronous External Memory Interface (EMIF) Figure 27 Reserved CS5ECC CS4ECC R/W-0 CS5NAND CS4NAND R/W-0 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table CS3ECC CS2ECC R/W-0 R/W-0 R/W-0 CS3NAND CS2NAND...

  • Page 61: Nand Flash Status Register (Nandfsr)

    16-bit NAND Flash, P1O, P2O, P4O, and P8O bits are column parities; P16O to P2048O bits are row parities. SPRUEQ7C – February 2010 Submit Documentation Feedback Figure 28 Reserved Reserved Figure 29 Asynchronous External Memory Interface (EMIF) Copyright © 2010, Texas Instruments Incorporated Registers and described in Table WAITST and described in Table 42. For 8-bit...

  • Page 62: Nand Flash N Ecc Register (Nandeccn)

    ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. Asynchronous External Memory Interface (EMIF) P2048O P16O P2048E P16E Copyright © 2010, Texas Instruments Incorporated www.ti.com P1024O P512O P256O P1024E P512E P256E SPRUEQ7C –...

  • Page 63: Appendix A Revision History

    Figure 1 Changed figure. Table 1 Changed table. Figure 2 Changed figure. Section 2.5.6.2 Changed paragraph. Figure 8 Changed figure. SPRUEQ7C – February 2010 Submit Documentation Feedback Table 43. Document Revision History Copyright © 2010, Texas Instruments Incorporated Revision History...

  • Page 64: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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