Receive Interrupt Status (Masked) Register (Rxintstatmasked); Receive Interrupt Status (Masked) Register (Rxintstatmasked) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)

The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in
described in Table
Figure 54. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
31
15
7 6
RX7PEND RX6PEND
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
Bit Field Value
31-8 Reserved 0
7 RX7PEND 0-1
6 RX6PEND 0-1
5 RX5PEND 0-1
4 RX4PEND 0-1
3 RX3PEND 0-1
2 RX2PEND 0-1
1 RX1PEND 0-1
0 RX0PEND 0-1
SPRUEQ6 – December 2007
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53.
5 4
RX5PEND RX4PEND
R-0 R-0
Description
Reserved
RX7PEND masked interrupt read
RX6PEND masked interrupt read
RX5PEND masked interrupt read
RX4PEND masked interrupt read
RX3PEND masked interrupt read
RX2PEND masked interrupt read
RX1PEND masked interrupt read
RX0PEND masked interrupt read
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Reserved
R-0
Reserved
R-0
3 2
RX3PEND RX2PEND
R-0 R-0
Figure 54 and
16
8
1 0
RX1PEND RX0PEND
R-0 R-0
97