Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear); Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in
Figure 36 and described in
Figure 36. MDIO User Command Complete Interrupt Mask Clear Register
31
15
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Bit Field
31-2 Reserved
1-0 USERINTMASKCLEAR
SPRUEQ6 – December 2007
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Table 34.
(USERINTMASKCLEAR)
Reserved
R-0
Reserved
R-0
Field Descriptions
Value Description
0 Reserved
0-3h MDIO user command complete interrupt mask clear for USERINTMASKED[1:0],
respectively. Setting a bit to 1 will disable further user command complete interrupts
for that particular USERACCESS register. USERINTMASKCLEAR[0] and
USERINTMASKCLEAR[1] correspond to USERACCESS0 and USERACCESS1,
respectively. Writing a 0 to this register has no effect.
0 MDIO user command complete interrupts for the MDIO user access register n
(USERACCESSn) are enabled.
1 MDIO user command complete interrupts for the MDIO user access register n
(USERACCESSn) are disabled.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
MDIO Registers
16
2 1 0
USERINTMASKCLEAR
R/W1C-0
79