Mac Interrupt Mask Set Register (Macintmaskset); Mac Interrupt Mask Clear Register (Macintmaskclear); Mac Interrupt Mask Set Register (Macintmaskset) Field Descriptions; Mac Interrupt Mask Clear Register (Macintmaskclear) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)

The MAC interrupt mask set register (MACINTMASKSET) is shown in
Table 58.
31
15
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset
Table 58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
Bit Field
31-2 Reserved
1 HOSTMASK
0 STATMASK

5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in
Table 59.
Figure 60. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
31
15
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
Bit Field
31-2 Reserved
1 HOSTMASK
0 STATMASK
SPRUEQ6 – December 2007
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Figure 59. MAC Interrupt Mask Set Register (MACINTMASKSET)
Reserved
R-0
Value Description
0 Reserved
0-1 Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0-1 Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Reserved
R-0
Value Description
0 Reserved
0-1 Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0-1 Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Reserved
R-0
Reserved
R-0
Figure 59 and described in
2 1
HOSTMASK STATMASK
R/W1S-0 R/W1S-0
Figure 60 and described in
2 1
HOSTMASK STATMASK
R/W1C-0 R/W1C-0
16
0
16
0
101