Receive Unicast Clear Register (Rxunicastclear); Receive Unicast Clear Register (Rxunicastclear) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Ethernet Media Access Controller (EMAC) Registers

5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)

The receive unicast clear register (RXUNICASTCLEAR) is shown in
Table 62.
31
15
7 6
RXCH7EN RXCH6EN
R/W1C-0 R/W1C-0
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
Bit Field Value
31-8 Reserved 0
7 RXCH7EN 0-1
6 RXCH6EN 0-1
5 RXCH5EN 0-1
4 RXCH4EN 0-1
3 RXCH3EN 0-1
2 RXCH2EN 0-1
1 RXCH1EN 0-1
0 RXCH0EN 0-1
106 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 63. Receive Unicast Clear Register (RXUNICASTCLEAR)
5 4
RXCH5EN RXCH4EN
R/W1C-0 R/W1C-0
Description
Reserved
Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
Figure 63
Reserved
R-0
Reserved
R-0
3 2
RXCH3EN RXCH2EN
R/W1C-0 R/W1C-0
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and described in
16
8
1 0
RXCH1EN RXCH0EN
R/W1C-0 R/W1C-0
SPRUEQ6 – December 2007
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