Emac Module; Emac Module Block Diagram - Texas Instruments TMS320DM646x User Manual

Architecture
2.8

EMAC Module

This section discusses the architecture and basic function of the EMAC module.
2.8.1 EMAC Module Components
The EMAC module
(MII) and interfaces to the system core through the EMAC control module. The EMAC consists of the
following logical components:
The receive path includes: receive DMA engine, receive FIFO, and MAC receiver
The transmit path includes: transmit DMA engine, transmit FIFO, and MAC transmitter
Statistics logic
State RAM
Interrupt controller
Control registers and logic
Clock and reset logic
Configuration bus
EMAC
control
module
Configuration bus
2.8.1.1 Receive DMA Engine
The receive DMA engine is the interface between the receive FIFO and the system core. It interfaces to
the CPU through the bus arbiter in the EMAC control module. This DMA engine is totally independent of
the device DMA.
2.8.1.2 Receive FIFO
The receive FIFO consists of 68 cells of 64 bytes each and associated control logic. The FIFO buffers
receive data in preparation for writing into packet buffers in device memory, and also enable receive FIFO
flow control.
38 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
(Figure 11) interfaces to the outside world through the Media Independent Interface
Figure 11. EMAC Module Block Diagram
Clock and
reset logic
Receive
DMA engine
Interrupt
controller
Transmit
DMA engine
Control
registers
Receive MAC
FIFO receiver
State
Statistics
RAM
Transmit MAC
FIFO transmitter
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SPRUEQ6 – December 2007
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