Table of Contents
Advertisement
www.ti.com
2.5.5.21
No Match (NOMATCH) Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet did not pass any of the
EMAC's address match criteria and was not discarded because the RXCAFEN bit was set in the
RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the
EMAC is in promiscuous mode.
2.6
EMAC Control Module
The basic functions of the EMAC control module
to the rest of the system, and to provide for a local memory space to hold EMAC packet buffer descriptors.
Local memory is used to help avoid contention to device memory spaces. Other functions include the bus
arbiter, and interrupt control and pacing logic control.
Transmit and Receive
Configuration bus
2.6.1
Internal Memory
The EMAC control module includes 8K bytes of internal memory. The internal memory block is essential
for allowing the EMAC to operate more independently of the CPU. It also prevents memory underflow
conditions when the EMAC issues read or write requests to descriptor memory. (Memory accesses to
read or write the actual Ethernet packet data are protected by the EMAC's internal FIFOs).
A descriptor is a 16-byte memory structure that holds information about a single Ethernet packet buffer,
which may contain a full or partial Ethernet packet. Thus with the 8K memory block provided for descriptor
storage, the EMAC module can send and received up to a combined 512 packets before it needs to be
serviced by application or driver software.
2.6.2
Bus Arbiter
The EMAC control module bus arbiter operates transparently to the rest of the system. It is used:
To arbitrate between the CPU and EMAC buses for access to internal descriptor memory.
To arbitrate between internal EMAC buses for access to system memory.
SPRUEQ6 – December 2007
Submit Documentation Feedback
Figure 9. EMAC Control Module Block Diagram
DMA Controllers
bus switches
EMAC interrupts
MDIO interrupts
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
(Figure
9) are to interface the EMAC and MDIO modules
Arbiter and
CPU
8K byte
descriptor
memory
Configuration
registers
Interrupt
control and
pacing logic
Architecture
4 interrupts
to ARM
31
Advertisement
Table of Contents
