Mac Address High Bytes Register (Macaddrhi); Mac Index Register (Macindex); Mac Address High Bytes Register (Macaddrhi) Field Descriptions; Mac Index Register (Macindex) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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5.44 MAC Address High Bytes Register (MACADDRHI)

The MAC address high bytes register (MACADDRHI) is shown in
31
MACADDR2
15
MACADDR4
LEGEND: R/W = Read/Write; -n = value after reset
Table 83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions
Bit Field
31-24 MACADDR2
23-16 MACADDR3
15-8 MACADDR4
7-0 MACADDR5

5.45 MAC Index Register (MACINDEX)

The MAC index register (MACINDEX) is shown in
31
15
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Bit Field Value
31-3 Reserved 0
2-0 MACINDEX 0-7h
SPRUEQ6 – December 2007
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Figure 84. MAC Address High Bytes Register (MACADDRHI)
R/W-0
R/W-0
Value Description
0-FFh MAC source address bits 23-16 (byte 2)
0-FFh MAC source address bits 31-24 (byte 3)
0-FFh MAC source address bits 39-32 (byte 4)
0-FFh MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0.
Therefore, only unicast addresses are represented in the address table.
Figure 85. MAC Index Register (MACINDEX)
Reserved
R-0
Table 84. MAC Index Register (MACINDEX) Field Descriptions
Description
Reserved
MAC address index. The host must write the index into the RX ADDR RAM in the MACINDEX field,
followed by the upper 32-bits of address, followed by the lower 16-bits of address (with control bits). The
53-bit indexed RAM location is written when the low location is written. All 32 address RAM locations
must be initialized prior to enabling packet reception.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Figure 84
24 23
8 7
Figure 85 and described in
Reserved
R-0
and described in Table
MACADDR3
R/W-0
MACADDR5
R/W-0
Table 84.
3 2
MACINDEX
R/W-0
83.
16
0
16
0
121