A7.1 About The L2 Memory System - ARM Cortex-A35 Technical Reference Manual

A7.1 About the L2 memory system
In most configurations, the L2 memory system consists of an integrated SCU that connects the cores in a
cluster, an optional, tightly-coupled L2 cache, and an optional ACP interface. In single core, AXI
configurations that do not include CPU cache protection, ACP, or an L2 cache, the SCU is replaced with
a more area-efficient mini-SCU.
The same system register control bit enables the L1 data cache and the L2 cache.
SCU
mini-SCU
100236_0100_00_en
The SCU maintains coherency between the L1 and L2 data caches in the processor. It also
arbitrates requests for the L2 cache and the AXI, ACE, or CHI master interface.
A coherent request from a core is one that checks for data in the L1 data caches and, if present,
the L2 cache. The SCU might send a request to another core to retrieve or invalidate data, or
both, depending on the type of coherent request. This request is referred to as a snoop request. If
the processor is implemented with an ACE or CHI master interface then the SCU can issue
coherent requests on the master interface, which might result in snoop requests being sent to
other masters in the system. The SCU might also receive snoop requests from other masters.
The SCU can handle direct cache-to-cache transfers between cores without having to read or
write any data to the external memory system. Cache line migration enables dirty cache lines to
be moved between cores, and there is no requirement to write back transferred cache line data to
the external memory system.
Each core has tag and dirty RAMs that contain the state of the cache line in the L1 data cache.
Rather than sending a snoop request to each core to access these for each coherent request, the
SCU contains a set of duplicate tags that allows it to check the contents of each L1 data cache.
The duplicate tags filter coherent requests so that a snoop request is only sent to a core if the
coherent request hits in the corresponding duplicate tags. The duplicate tags are also used to
filter snoop requests from the external memory system. This allows the cores and the system to
function efficiently even with a high volume of requests.
The SCU does not support hardware management of coherency of the instruction caches.
Instruction cache linefills perform coherent reads, however, there is no coherency management
of data held in the instruction cache.
The mini-SCU replaces the SCU in certain uniprocessor configurations that do not require data
cache coherency with other masters in the system. That is, implementations that are configured
to have a single CPU, no L2 cache, no CPU cache protection, and an AXI interface. The mini-
SCU bridges between the master interface of the core and the AXI master interface of the
processor.
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
A7 L2 Memory System

A7.1 About the L2 memory system

A7-98