ARM Cortex-A35 Technical Reference Manual page 7

Chapter A8
Chapter A9
Chapter A10
Chapter A11
Chapter A12
Part B
Chapter B1
100236_0100_00_en
AXI Master Interface
A8.1 About the AXI master interface ..................................... ..................................... A8-106
A8.2 AXI privilege information .......................................... .......................................... A8-107
A8.3 AXI transactions .................................................................................................. A8-108
A8.4 Attributes of the AXI master interface .................................................................. A8-110
ACE Master Interface
A9.1 About the ACE master interface .......................................................................... A9-114
A9.2 ACE configurations .............................................................................................. A9-115
A9.3 ACE privilege information .................................................................................... A9-116
A9.4 ACE transactions ................................................ ................................................ A9-117
A9.5 Attributes of the ACE master interface ................................................................ A9-120
A9.6 Snoop channel properties ......................................... ......................................... A9-122
A9.7 AXI compatibility mode ........................................................................................ A9-123
CHI Master Interface
A10.1 About the CHI master interface .................................... .................................... A10-126
A10.2 CHI configurations .............................................. .............................................. A10-127
A10.3 Attributes of the CHI master interface ............................... ............................... A10-128
A10.4 CHI channel properties .......................................... .......................................... A10-130
A10.5 CHI transactions ................................................................................................ A10-131
ACP Slave Interface
A11.1 About the ACP ................................................. ................................................. A11-136
A11.2 Transfer size support ............................................ ............................................ A11-137
A11.3 ACP performance .............................................................................................. A11-138
A11.4 ACP user signals ............................................... ............................................... A11-139
GIC CPU Interface
A12.1 Bypassing the GIC CPU Interface .................................. .................................. A12-142
A12.2 Memory map for the GIC CPU interface ............................. ............................. A12-143
Register Descriptions
AArch32 system registers
B1.1 AArch32 register summary .................................................................................. B1-150
B1.2 c0 registers .......................................................................................................... B1-152
B1.3 c1 registers .......................................................................................................... B1-155
B1.4 c2 registers .......................................................................................................... B1-156
B1.5 c3 registers .......................................................................................................... B1-157
B1.6 c4 registers .......................................................................................................... B1-158
B1.7 c5 registers .......................................................................................................... B1-159
B1.8 c6 registers .......................................................................................................... B1-160
B1.9 c7 registers .......................................................................................................... B1-161
B1.10 c7 system operations .......................................................................................... B1-162
B1.11 c8 system operations .......................................................................................... B1-165
B1.12 c9 registers .......................................................................................................... B1-167
B1.13 c10 registers ........................................................................................................ B1-168
B1.14 c11 registers ........................................................................................................ B1-169
B1.15 c12 registers ........................................................................................................ B1-170
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