B2.68 Aarch32 Processor Feature Register 1, El1 - ARM Cortex-A35 Technical Reference Manual

B2.68 AArch32 Processor Feature Register 1, EL1
The ID_PFR1_EL1 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
GIC CPU, [31:28]
[27:20]
GenTimer, [19:16]
Virtualization, [15:12]
MProgMod, [11:8]
Security, [7:4]
100236_0100_00_en
Provides information about the programmers model and architecture extensions supported by
the processor.
This register is accessible as follows:
ID_PFR1_EL1 is architecturally mapped to AArch32 register ID_PFR1. See
Feature Register 1 on page
ID_PFR1_EL1 is a 32-bit register.
31 28 27 24
GIC CPU Reserved
GIC CPU support:
GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x0
GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
0x1
Reserved, .
RES0
Generic Timer support:
Generic Timer supported.
0x1
Virtualization support:
Virtualization implemented.
0x1
M profile programmers' model support:
Not supported.
0x0
Security support:
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B2.68 AArch32 Processor Feature Register 1, EL1

EL0 EL1
(NS)
- RO
B1-291.
23 20 19 16 15
GenTimer
Virtualization
Figure B2-41 ID_PFR1_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
EL2 EL3
EL1
(S) (SCR.NS = 1)
RO RO RO
B1.85 Processor
12 11 8 7
MProgMod Security
EL3
(SCR.NS = 0)
RO
4 3 0
ProgMod
B2-477