B1.68 Hyp Syndrome Register - ARM Cortex-A35 Technical Reference Manual

B1.68 Hyp Syndrome Register
The HSR characteristics are:
Purpose
Usage constraints
Configurations
Attributes
EC, [31:26]
IL, [25]
ISS, [24:0]
100236_0100_00_en
Holds syndrome information for an exception taken to Hyp mode.
This register is accessible as follows:
HSR is architecturally mapped to AArch64 register ESR_EL2. See
Register, EL2 on page B2-425.
This register is accessible only at EL2 or EL3.
HSR is a 32-bit register.
31 26 25 24
EC
Exception class. The exception class for the exception that is taken in Hyp mode. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Instruction length. See the Arm
architecture profile for more information.
Instruction specific syndrome. See the Arm
A architecture profile for more information. The interpretation of this field depends on the value
of the EC field. See B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00 on page
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EL0 EL0 EL1
(NS) (S) (NS)
- - -
IL
Architecture Reference Manual Armv8, for Armv8-A
®
Architecture Reference Manual Armv8, for Armv8-
®
reserved.
Non-Confidential
B1 AArch32 system registers

B1.68 Hyp Syndrome Register

EL2 EL3
EL1
(S) (SCR.NS = 1)
- RW RW
B2.42 Exception Syndrome
ISS
Figure B1-24 HSR bit assignments
EL3
(SCR.NS = 0)
-
0
®
B1-228.
B1-258