ARM Cortex-A35 Technical Reference Manual page 528

CP15BEN, [5]
SA0, [4]
SA, [3]
C, [2]
A, [1]
M, [0]
To access the SCTLR_EL1:
MRS <Xt>, SCTLR_EL1 ; Read SCTLR_EL1 into Xt
MSR SCTLR_EL1, <Xt> ; Write Xt to SCTLR_EL1
Register access is encoded as follows:
100236_0100_00_en
T32EE is not implemented.
RES0
CP15 barrier enable. The possible values are:
CP15 barrier operations disabled. Their encodings are
0
CP15 barrier operations enabled. This is the reset value.
1
Enable EL0 stack alignment check. The possible values are:
Disable EL0 stack alignment check.
0
Enable EL0 stack alignment check. This is the reset value.
1
Enable SP alignment check. The possible values are:
Disable SP alignment check.
0
Enable SP alignment check. This is the reset value.
1
Cache enable. The possible values are:
Data and unified caches disabled. This is the reset value.
0
Data and unified caches enabled.
1
Alignment check enable. The possible values are:
Alignment fault checking disabled. This is the reset value.
0
Alignment fault checking enabled.
1
MMU enable. The possible values are:
EL1 and EL0 stage 1 MMU disabled. This is the reset value.
0
EL1 and EL0 stage 1 MMU enabled.
1
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
Table B2-84 SCTLR_EL1 access encoding
reserved.
Non-Confidential
B2 AArch64 system registers
B2.90 System Control Register, EL1
.
UNDEFINED
op0 op1 CRn CRm op2
11 000 0001 0000 000
B2-528