C11.21 Counter Reload Value Registers 0-1 - ARM Cortex-A35 Technical Reference Manual

C11.21 Counter Reload Value Registers 0-1
The TRCCNTRLDVRn characteristics are:
Purpose
Usage constraints
Configurations
Attributes
[31:16]
VALUE, [15:0]
The TRCCNTRLDVRn registers can be accessed through the external debug interface, offsets:
TRCCNTRLDVR0
TRCCNTRLDVR1
100236_0100_00_en
Defines the reload value for the counter.
Accepts writes only when the trace unit is disabled.
Available in all configurations.
See C11.1 ETM register summary on page
31
RES
Reserved, .
RES0
Defines the reload value for the counter. This value is loaded into the counter each time the
reload event occurs.
.
0x140
.
0x144
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
C11-733.
16 15
0
Figure C11-20 TRCCNTRLDVRn bit assignments
reserved.
Non-Confidential
C11 ETM registers

C11.21 Counter Reload Value Registers 0-1

VALUE
0
C11-760