A5.4 Disabling A Cache - ARM Cortex-A35 Technical Reference Manual

A5.4 Disabling a cache
In the AArch64 execution state, disabling the instruction cache has no effect. Instruction fetches continue
to be cached and cache maintenance operations execute normally.
In the AArch32 execution state, when the instruction cache is disabled:
• Instruction fetches do not access the L1 instruction cache or the L2 unified cache.
• Instruction cache maintenance operations execute normally.
• All instruction fetches to cacheable memory are treated as if they were non-cacheable. This means
that instruction fetches might not be coherent with caches in other cores and software must take
account of this.
When the data cache is disabled:
• Load and store instructions do not access the L1 data cache or L2 unified cache.
• Instruction fetches do not access the L2 unified cache.
• Data cache maintenance operations to the L1 data cache and the L2 unified cache execute normally.
• All load and store instructions to cacheable memory are treated as if they were non-cacheable. This
means that they are not coherent with the caches in this core or the caches in other cores and software
must take account of this.
You cannot disable the L1 data cache and the L2 unified cache independently because the same enable
bit controls both of them.
If the instruction cache is enabled and the data cache is disabled, then instruction fetches to cacheable
memory continue to access the L1 instruction cache but they do not access the L2 unified cache.
Related information
B1.105 System Control Register on page B1-331
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A5 Cache Behavior and Cache Protection

A5.4 Disabling a cache

A5-81