ARM Cortex-A35 Technical Reference Manual page 544

TG0, [15:14]
SH0, [13:12]
ORGN0, [11:10]
IRGN0, [9:8]
[7:6]
T0SZ, [5:0]
100236_0100_00_en
32 bits, 4GB.
0b000
36 bits, 64GB.
0b001
40 bits, 1TB.
0b010
Other values are reserved.
TTBR0_EL3 granule size. The possible values are:
4KB.
0b00
16KB.
0b10
64KB.
0b01
Reserved.
0b11
All other values are not supported.
Shareability attribute for memory associated with translation table walks using TTBR0_EL3.
The possible values are:
Non-shareable.
0b00
Reserved.
0b01
Outer shareable.
0b10
Inner shareable.
0b11
Outer cacheability attribute for memory associated with translation table walks using
TTBR0_EL3.
The possible values are:
Normal memory, Outer Non-cacheable.
0b00
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b01
Normal memory, Outer Write-Through Cacheable.
0b10
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
0b11
Inner cacheability attribute for memory associated with translation table walks using
TTBR0_EL3.
The possible values are:
Normal memory, Inner Non-cacheable.
0b00
Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b01
Normal memory, Inner Write-Through Cacheable.
0b10
Normal memory, Inner Write-Back no Write-Allocate Cacheable.
0b11
Reserved, .
RES0
Size offset of the memory region addressed by TTBR0_EL3. The region size is 2
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
B2 AArch64 system registers
B2.96 Translation Control Register, EL3
(64-T0SZ)
bytes.
B2-544