ARM Cortex-A35 Technical Reference Manual page 8

Table of Contents

Advertisement

100236_0100_00_en
B1.16
c13 registers ........................................................................................................ B1-172
B1.17
c14 registers ........................................................................................................ B1-173
B1.18
c15 registers ........................................................................................................ B1-174
B1.19
64-bit registers .................................................. .................................................. B1-175
B1.20
AArch32 Identification registers ..................................... ..................................... B1-176
B1.21
AArch32 Virtual memory control registers ............................. ............................. B1-178
B1.22
AArch32 Fault handling registers ........................................................................ B1-179
B1.23
AArch32 Other System control registers .............................. .............................. B1-180
B1.24
AArch32 Address registers ........................................ ........................................ B1-181
B1.25
AArch32 Thread registers ......................................... ......................................... B1-182
B1.26
AArch32 Performance monitor registers .............................. .............................. B1-183
B1.27
AArch32 Secure registers ......................................... ......................................... B1-185
B1.28
AArch32 Virtualization registers .......................................................................... B1-186
B1.29
AArch32 GIC system registers ............................................................................ B1-188
B1.30
AArch32 Generic Timer registers ........................................................................ B1-190
B1.31
AArch32 Implementation defined registers ............................ ............................ B1-191
B1.32
Auxiliary Control Register .................................................................................... B1-193
B1.33
Auxiliary Data Fault Status Register ................................. ................................. B1-195
B1.34
Auxiliary ID Register ............................................................................................ B1-196
B1.35
Auxiliary Instruction Fault Status Register ............................. ............................. B1-197
B1.36
Auxiliary Memory Attribute Indirection Register 0 ....................... ....................... B1-198
B1.37
Auxiliary Memory Attribute Indirection Register 1 ....................... ....................... B1-199
B1.38
Configuration Base Address Register ................................ ................................ B1-200
B1.39
Cache Size ID Register ........................................... ........................................... B1-201
B1.40
Cache Level ID Register .......................................... .......................................... B1-204
B1.41
Architectural Feature Access Control Register ......................... ......................... B1-206
B1.42
CPU Auxiliary Control Register ..................................... ..................................... B1-208
B1.43
CPU Extended Control Register .................................... .................................... B1-212
B1.44
CPU Memory Error Syndrome Register .............................................................. B1-214
B1.45
Cache Size Selection Register ............................................................................ B1-217
B1.46
Cache Type Register ............................................. ............................................. B1-219
B1.47
Domain Access Control Register ........................................................................ B1-221
B1.48
Data Fault Address Register ....................................... ....................................... B1-222
B1.49
Data Fault Status Register .................................................................................. B1-223
B1.50
DFSR with Short-descriptor translation table format ..................... ..................... B1-224
B1.51
DFSR with Long-descriptor translation table format ..................... ..................... B1-226
B1.52
Encoding of ISS[24:20] when HSR[31:30] is 0b00 .............................................. B1-228
B1.53
FCSE Process ID Register .................................................................................. B1-229
B1.54
Hyp Auxiliary Configuration Register ................................. ................................. B1-230
B1.55
Hyp Auxiliary Control Register ............................................................................ B1-231
B1.56
Hyp Auxiliary Data Fault Status Syndrome Register ..................... ..................... B1-233
B1.57
Hyp Auxiliary Instruction Fault Status Syndrome Register .................................. B1-234
B1.58
Hyp Auxiliary Memory Attribute Indirection Register 0 ........................................ B1-235
B1.59
Hyp Auxiliary Memory Attribute Indirection Register 1 ........................................ B1-236
B1.60
Hyp Architectural Feature Trap Register .............................. .............................. B1-237
B1.61
Hyp Configuration Register ........................................ ........................................ B1-240
B1.62
Hyp Configuration Register 2 .............................................................................. B1-246
B1.63
Hyp Debug Control Register ....................................... ....................................... B1-248
B1.64
Hyp Data Fault Address Register ........................................................................ B1-251
B1.65
Hyp Instruction Fault Address Register ............................... ............................... B1-252
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
8

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents