B2.57 Aarch32 Instruction Set Attribute Register 0, El1 - ARM Cortex-A35 Technical Reference Manual

B2.57 AArch32 Instruction Set Attribute Register 0, EL1
The ID_ISAR0_EL1 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
[31:28]
Divide, [27:24]
Debug, [23:20]
Coproc, [19:16]
CmpBranch, [15:12]
Bitfield, [11:8]
100236_0100_00_en
Provides information about the instruction sets implemented by the processor in AArch32.
This register is accessible as follows:
ID_ISAR0_EL1 is architecturally mapped to AArch32 register ID_ISAR0. See
B1.74 Instruction Set Attribute Register 0 on page
ID_ISAR0_EL1 is a 32-bit register.
31 28 27 24 23
0 Divide
RES
Reserved, .
RES0
Indicates the implemented Divide instructions:
• and
0x2 SDIV UDIV
• and
SDIV UDIV
Indicates the implemented Debug instructions:
.
0x1 BKPT
Indicates the implemented Coprocessor instructions:
None implemented, except for separately attributed by the architecture including
0x0
CP15, CP14, Advanced SIMD and floating-point.
Indicates the implemented combined Compare and Branch instructions in the T32 instruction
set:
and .
0x1 CBNZ CBZ
Indicates the implemented bit field instructions:
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B2.57 AArch32 Instruction Set Attribute Register 0, EL1

EL0 EL1
(NS)
- RO
B1-269.
20 19 16 15
Debug Coproc CmpBranch
Figure B2-30 ID_ISAR0_EL1 bit assignments
in the T32 instruction set.
in the A32 instruction set.
reserved.
Non-Confidential
B2 AArch64 system registers
EL2 EL3
EL1
(S) (SCR.NS = 1)
RO RO RO
12 11 8 7
Bitfield BitCount
EL3
(SCR.NS = 0)
RO
4 3 0
Swap
B2-455