B2.53 Aarch64 Memory Model Feature Register 0, El1 - ARM Cortex-A35 Technical Reference Manual

B2.53 AArch64 Memory Model Feature Register 0, EL1
The ID_AA64MMFR0_EL1 characteristics are:
Purpose
Usage constraints
Attributes
63
0
RES
[63:32]
TGran4, [31:28]
TGran64, [27:24]
TGran16, [23:20]
BigEndEL0, [19:16]
SNSMem, [15:12]
BigEnd, [11:8]
100236_0100_00_en
Provides information about the implemented memory model and memory management support
in the AArch64 Execution state.
This register is accessible as follows:
ID_AA64MMFR0_EL1 is a 64-bit register.
32 31 28 27 24 23
TGran4 TGran64
Reserved, .
RES0
Support for 4KB memory translation granule size:
Indicates that the 4KB granule is supported.
0x0
Support for 64KB memory translation granule size:
Indicates that the 64KB granule is supported.
0x0
Support for 16KB memory translation granule size:
Indicates that the 16KB granule is supported.
0x1
Mixed-endian support only at EL0.
RES0
Secure versus Non-secure Memory distinction:
Supports a distinction between Secure and Non-secure Memory.
0b0001
Mixed-endian configuration support:
Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits are RW.
0b0001
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B2.53 AArch64 Memory Model Feature Register 0, EL1

EL0 EL1
EL1
(NS) (S)
- RO RO
20 19 16 15
TGran16 BigEndEL0 SNSMem
Figure B2-27 ID_AA64MMFR0_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
EL2 EL3
EL3
(SCR.NS = 1) (SCR.NS = 0)
RO RO RO
12 11 8 7 4 3
BigEnd ASIDBits
0
PARange
B2-448