ARM Cortex-A35 Technical Reference Manual page 689

Chapter C10
PMU registers
This chapter describes the PMU registers.
It contains the following sections:
• C10.1 AArch32 PMU register summary on page
• C10.2 Performance Monitors Control Register on page
• C10.3 Performance Monitors Common Event Identification Register 0 on page
• C10.4 Performance Monitors Common Event Identification Register 1 on page
• C10.5 AArch64 PMU register summary on page
• C10.6 Performance Monitors Control Register, EL0 on page
• C10.7 Performance Monitors Common Event Identification Register 0, EL0 on page
• C10.8 Performance Monitors Common Event Identification Register 1, EL0 on page
• C10.9 Memory-mapped PMU register summary on page
• C10.10 Performance Monitors Configuration Register on page
• C10.11 Performance Monitors Peripheral Identification Registers on page
• C10.12 Performance Monitors Peripheral Identification Register 0 on page
• C10.13 Performance Monitors Peripheral Identification Register 1 on page
• C10.14 Performance Monitors Peripheral Identification Register 2 on page
• C10.15 Performance Monitors Peripheral Identification Register 3 on page
• C10.16 Performance Monitors Peripheral Identification Register 4 on page
• C10.17 Performance Monitors Peripheral Identification Register 5-7 on page
• C10.18 Performance Monitors Component Identification Registers on page
• C10.19 Performance Monitors Component Identification Register 0 on page
• C10.20 Performance Monitors Component Identification Register 1 on page
• C10.21 Performance Monitors Component Identification Register 2 on page
• C10.22 Performance Monitors Component Identification Register 3 on page
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