ARM Cortex-A35 Technical Reference Manual page 330

IRQ, [1]
NS, [0]
To access the SCR:
MRC p15,0,<Rt>,c1,c1,0 ; Read SCR into Rt
MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR
Register access is encoded as follows:
100236_0100_00_en
FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:
FIQs taken in FIQ mode. This is the reset value.
0
FIQs taken in Monitor mode.
1
IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:
IRQs taken in IRQ mode. This is the reset value.
0
IRQs taken in Monitor mode.
1
Non-secure bit. Except when the processor is in Monitor mode, this bit determines the security
state of the processor. The possible values are:
Processor is in secure state. This is the reset value.
0
Processor is in non-secure state.
1
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B1 AArch32 system registers
B1.104 Secure Configuration Register
Table B1-89 SCR access encoding
coproc opc1 CRn CRm opc2
1111 000 0001 0001 000
B1-330