ARM Cortex-A35 Technical Reference Manual page 708

Bit Event number Event mnemonic
[28] 0x1C
TTBR_WRITE_RETIRED
[27] 0x1B
INST_SPEC
[26] 0x1A
MEMORY_ERROR
[25] 0x19
BUS_ACCESS
[24] 0x18
L2D_CACHE_WB
[23] 0x17
L2D_CACHE_REFILL
[22] 0x16
L2D_CACHE
[21] 0x15
L1D_CACHE_WB
[20] 0x14
L1I_CACHE
[19] 0x13
MEM_ACCESS
[18] 0x12
BR_PRED
100236_0100_00_en
C10.7 Performance Monitors Common Event Identification Register 0, EL0
Description
TTBR write, architecturally executed, condition check pass - write to
translation table base:
0
Instruction speculatively executed:
1
Local memory error:
1
Bus access:
1
L2 Data cache Write-Back:
0
1
L2 Data cache refill:
0
1
L2 Data cache access:
0
1
L1 Data cache Write-Back:
1
L1 Instruction cache access:
1
Data memory access:
1
Predictable branch speculatively executed:
1
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Table C10-5 PMU common events (continued)
This event is not implemented.
This event is implemented.
This event is implemented.
This event is implemented.
This event is not implemented if the Cortex‑A35 processor has
been configured without an L2 cache.
This event is implemented if the Cortex‑A35 processor has
been configured with an L2 cache.
This event is not implemented if the Cortex‑A35 processor has
been configured without an L2 cache.
This event is implemented if the Cortex‑A35 processor has
been configured with an L2 cache.
This event is not implemented if the Cortex‑A35 processor has
been configured without an L2 cache.
This event is implemented if the Cortex‑A35 processor has
been configured with an L2 cache.
This event is implemented.
This event is implemented.
This event is implemented.
This event is implemented.
C10 PMU registers
C10-708