B2.88 Reset Vector Base Address Register, El3 - ARM Cortex-A35 Technical Reference Manual

B2.88 Reset Vector Base Address Register, EL3
The RVBAR_EL3 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
63
RVBA, [63:0]
To access the RVBAR_EL3:
MRS <Xt>, RVBAR_EL3 ; Read RVBAR_EL3 into Xt
Register access is encoded as follows:
100236_0100_00_en
Contains the address that execution starts from after reset when executing in the AArch64 state.
RVBAR_EL3 is part of the Reset management registers functional group.
This register is accessible as follows:
There is no configuration information.
RVBAR_EL3 is a 64-bit register.
Reset Vector Base Address. The address that execution starts from after reset when executing in
64-bit state. Bits[1:0] of this register are
are because the address must be within the physical address size supported by the
0x000000
processor.
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EL0 EL1
(NS)
- -
Reset Vector Base Address
Figure B2-59 RVBAR_EL3 bit assignments
, as this address must be aligned, and bits [63:40]
0b00
Table B2-82 RVBAR_EL3 access encoding
reserved.
Non-Confidential
B2 AArch64 system registers

B2.88 Reset Vector Base Address Register, EL3

EL2 EL3
EL1
(S) (SCR.NS = 1)
- - RO
op0 op1 CRn CRm op2
11 110 1100 0000
EL3
(SCR.NS = 0)
RO
0
001
B2-521