B2.94 Translation Control Register, El1 - ARM Cortex-A35 Technical Reference Manual

B2.94 Translation Control Register, EL1
The TCR_EL1 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
63
0
RES
[63:39]
TBI1, [38]
TBI0, [37]
AS, [36]
100236_0100_00_en
Determines which Translation Base Registers defines the base address register for a translation
table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds
cacheability and shareability information.
TCR_EL1 is part of the Virtual memory control registers functional group.
This register is accessible as follows:
TCR_EL1 is architecturally mapped to AArch32 register TTBCR(NS). See
Table Base Control Register on page
TCR_EL1 is a 64-bit register.
39 38 37 36 35 34 32 31 30 29 28
IPS TG1 SH1
0
RES
AS
TBI0
TBI1
Reserved, .
RES0
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match
for the TTBR1_EL1 region. The possible values are:
Top byte used in the address calculation.
0
Top byte ignored in the address calculation.
1
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match
for the TTBR0_EL1 region. The possible values are:
Top byte used in the address calculation.
0
Top byte ignored in the address calculation.
1
ASID size. The possible values are:
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
EL0 EL1
(NS)
- RW
B1-341.
27 26 25 24 23 22 21
T1SZ
ORGN1
IRGN1
EPD1
A1
Figure B2-65 TCR_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers

B2.94 Translation Control Register, EL1

EL2 EL3
EL1
(S) (SCR.NS = 1)
RW RW RW
B1.110 Translation
16 15 14 13 12 11 10 9 8 7
TG0 SH0
EL3
(SCR.NS = 0)
RW
6 5 0
T0SZ
0
RES
EPD0
IRGN0
ORGN0
B2-536