C11.34 Id Register 2 - ARM Cortex-A35 Technical Reference Manual

C11.34 ID Register 2
The TRCIDR2 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
[31:29]
CCSIZE, [28:25]
DVSIZE, [24:20]
DASIZE, [19:15]
VMIDSIZE, [14:10]
CIDSIZE, [9:5]
IASIZE, [4:0]
100236_0100_00_en
Returns the maximum size of the following parameters in the trace unit:
• Cycle counter.
• Data value.
• Data address.
• VMID.
• Context ID.
• Instruction address.
There are no usage constraints.
Available in all configurations.
See C11.1 ETM register summary on page
31 29 28 25 24
0 CCSIZE
RES
Reserved, .
RES0
Size of the cycle counter in bits minus 12:
The cycle counter is 12 bits in length.
0x0
Data value size in bytes:
Data value tracing is not implemented.
0x00
Data address size in bytes:
Data address tracing is not implemented.
0x00
Virtual Machine ID size:
Virtual Machine ID is 8 bits.
0x1
Context ID size in bytes:
Maximum of 32-bit Context ID size.
0x4
Instruction address size in bytes:
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
C11-733.
20 19 15 14
DVSIZE DASIZE
Figure C11-33 TRCIDR2 bit assignments
reserved.
Non-Confidential
C11 ETM registers

C11.34 ID Register 2

10 9 5 4
VMIDSIZE CIDSIZE
0
IASIZE
C11-776