C10.15 Performance Monitors Peripheral Identification Register 3 - ARM Cortex-A35 Technical Reference Manual

C10.15 Performance Monitors Peripheral Identification Register 3

The PMPIDR3 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
[31:8]
REVAND, [7:4]
CMOD, [3:0]
The PMPIDR3 can be accessed through the external debug interface, offset
100236_0100_00_en
Provides information to identify a Performance Monitor component.
The PMPIDR3 can be accessed through the external debug interface.
The accessibility to the PMPIDR3 by condition code is:
C2.2 External register access permissions to the PMU registers on page C2-587
condition codes.
The PMPIDR3 is in the Debug power domain.
See the register summary in
31
Reserved, .
RES0
Part minor revision.
0x0
Customer modified.
0x0
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C10.15 Performance Monitors Peripheral Identification Register 3
Off DLK OSLK EPMAD SLK Default
-
C10.9 Memory-mapped PMU register summary on page
0
RES
Figure C10-11 PMPIDR3 bit assignments
reserved.
Non-Confidential
C10 PMU registers
- - - RO
describes the
8 7 4
REVAND
.
0xFEC
RO
C10-714.
3 0
CMOD
C10-723