C11.57 Device Affinity Register 0 - ARM Cortex-A35 Technical Reference Manual

C11.57 Device Affinity Register 0
The TRCDEVAFF0 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
M, [31]
U, [30]
[29:25]
MT, [24]
100236_0100_00_en
Provides an additional core identification mechanism for scheduling purposes in a cluster.
TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
This register is accessible as follows:
The TRCDEVAFF0 is:
• Architecturally mapped to the AArch64 MPIDR_EL1[31:0] register. See
Register, EL1 on page B2-510.
• Architecturally mapped to external TRCDEVAFF0 register.
There is one copy of this register that is used in both Secure and Non-secure states.
TRCDEVAFF0 is a 32-bit register.
31 30 29 25 24
M U 0
RES
MT
Reserved, .
RES1
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
Processor is part of a multiprocessor system. This is the value for implementations
0
with more than one core, and for implementations with an ACE or CHI master
interface.
Processor is part of a uniprocessor system. This is the value for single core
1
implementations with an AXI master interface.
Reserved, .
RES0
Indicates whether the lowest level of affinity consists of logical cores that are implemented
using a multi-threading type approach. This value is:
Performance of cores at the lowest affinity level is largely independent.
0
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EL0 EL0 EL1 EL1
(NS) (S) (NS) (S)
- - RO RO
23 16 15
Aff2
Figure C11-56 TRCDEVAFF0 bit assignments
reserved.
Non-Confidential
C11 ETM registers

C11.57 Device Affinity Register 0

EL2 EL3
EL3
(SCR.NS = 1) (SCR.NS = 0)
RO RO RO
B2.83 Main ID
8 7
Aff1 Aff0
0
C11-804