A.19
CTI interface signals
The processor supports various cross-trigger signals when it implements the CTI.
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Signal
Direction Description
CTICHIN[3:0]
Input
CTICHOUTACK[3:0] Input
CTICHOUT[3:0]
Output
CTICHINACK[3:0]
Output
CISBYPASS
Input
CIHSBYPASS[3:0]
Input
CTIIRQ[CN:0]
Output
CTIIRQACK[CN:0]
Input
A Signal Descriptions
A.19 CTI interface signals
Table A-47 CTI interface signals
Channel In
Channel Out acknowledge
Channel Out
Channel In acknowledge
Channel interface sync bypass
Channel interface H/S bypass
CTI interrupt, active-HIGH
CTI interrupt acknowledge
Appx-A-877
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