B1.78 Instruction Set Attribute Register 4 - ARM Cortex-A35 Technical Reference Manual

B1.78 Instruction Set Attribute Register 4
The ID_ISAR4 characteristics are:
Purpose
Usage constraints
Configurations
Attributes
SWP_frac, [31:28]
PSR_M, [27:24]
SynchPrim_frac, [23:20]
Barrier, [19:16]
100236_0100_00_en
Provides information about the instruction sets implemented by the processor in AArch32.
This register is accessible as follows:
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR5. See:
• B1.74 Instruction Set Attribute Register 0 on page B1-269
• B1.75 Instruction Set Attribute Register 1 on page B1-271
• B1.76 Instruction Set Attribute Register 2 on page B1-273
• B1.77 Instruction Set Attribute Register 3 on page B1-275
• B1.79 Instruction Set Attribute Register 5 on page B1-279
ID_ISAR4 is architecturally mapped to AArch64 register ID_ISAR4_EL1. See
Instruction Set Attribute Register 4, EL1 on page
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR4 is a 32-bit register.
31 28 27 24 23
SWP_frac PSR_M
SynchPrim_frac
Indicates support for the memory system locking the bus for
and instructions not implemented.
0x0 SWP SWPB
Indicates the implemented M profile instructions to modify the PSRs:
None implemented.
0x0
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented
Synchronization Primitive instructions:
• The and
0x0 LDREX
• The ,
CLREX LDREXB
• The and
LDREXD
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EL0 EL0 EL1
(NS) (S) (NS)
- - RO
B2-463.
20 19 16 15
Barrier
Figure B1-33 ID_ISAR4 bit assignments
instructions.
STREX
, , , and
LDREXH STREXB
instructions.
STREXD
reserved.
Non-Confidential
B1 AArch32 system registers

B1.78 Instruction Set Attribute Register 4

EL2 EL3
EL1
(S) (SCR.NS = 1)
RO RO RO
B2.61 AArch32
12 11 8 7
SMC Writeback WithShifts
or instructions:
SWP SWPB
instructions.
STREXH
EL3
(SCR.NS = 0)
RO
4 3 0
Unpriv
B1-277