ARM Cortex-A35 Technical Reference Manual page 306

[28:3]
L2 dynamic retention control, [2:0]
To access the L2ECTLR:
MRC p15, 1, <Rt>, c9, c0, 3; Read L2ECTLR into Rt
MCR p15, 1, <Rt>, c9, c0, 3; Write Rt to L2ECTLR
Register access is encoded as follows:
100236_0100_00_en
Reserved, .
RES0
L2 dynamic retention control. The possible values are:
L2 dynamic retention disabled. This is the reset value.
0b000
2 Generic Timer ticks required before retention entry.
0b001
8 Generic Timer ticks required before retention entry.
0b010
32 Generic Timer ticks required before retention entry.
0b011
64 Generic Timer ticks required before retention entry.
0b100
128 Generic Timer ticks required before retention entry.
0b101
256 Generic Timer ticks required before retention entry.
0b110
512 Generic Timer ticks required before retention entry.
0b111
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Table B1-74 L2ECTLR access encoding
reserved.
Non-Confidential
B1 AArch32 system registers
B1.93 L2 Extended Control Register
coproc opc1 CRn CRm opc2
1111 001 1001 0000 011
B1-306