Tsei Data Register (Sedr) - Toshiba TX79 Series User Manual

15.8.3

TSEI Data Register (SEDR)

This register is the data register of the TSEI system.
7
data7
R/W
Reset: 0
When the TSEI system is configured as a master, transfers are started by a software write to
the SEDR register.
15.8.4 TSEI Data Direction Register (DDCR)
This register may be read or written to at any time and is used to enable or disable the input
and output pins of the TSEI system.
7
-
-
Reset: 0
TSS_n: Slave Select (low active)
When TSEI is enabled as a slave, the TSS_n pin is the slave select input, regardless of the
value of the DDCR register.
When TSEI is enabled as a master, the function of the TSS_n pin depends on the value of
DDCR bit 5.
0: The TSS_n pin is used as an input to detect mode fault errors. A low TSS_n pin
indicates that some other device in a multiple master environment is acting as a master
and is trying to select this device as a slave. To prevent harmful contention between
output drivers, a mode fault is generated which will disable the module and tri-state all
output pins.
1: No mode fault will be generated.
TSCLK: Serial Clock Signal
When TSEI is enabled as a slave, the TSCLK pin will function as an input, regardless of the
value in the DDCR register.
When TSEI is acting as a master, bit 4 in the DDCR register must be asserted to enable the
TSCLK output.
TSDMOSI: Master Output, Slave Input
When the TSEI system is enabled as a slave, the TSDMOSI pin acts as the slave serial data
input regardless of the state of DDCR3.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 15: Serial Port Interface
6 5 4
data6 data5 data4
R/W R/W R/W
0 0 0
6 5 4
- TSS_n TSCLK
- R/W R/W
0 0 0
3 2 1
data3 data2 data1
R/W R/W R/W
0 0 0
3 2
MOSI MISO
R/W R/W
0 0
15-16
0
data0 2
h
R/W
0
1 0
- - 3
h
- -
0 0