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12.4.3
Transmit Descriptors
The format of the Transmit Descriptors is shown below. It is made of two doublewords, and
the fields are described in more detail in Table 12-35.
OWN
Byte-Count Buffer 1
Buffer Address 1
12.4.3.1 Transmit Descriptor
The Transmit Descriptor contains the transmit frame status, the frame length, and the
Descriptor ownership information in the first word (Word 0). The 32 bits of two Transmit
Buffer Addresses is in the second word (Word 1). Bits [31:0] in Word 0 are read only. Bits
[30:0] are valid only when TxEOF is set and OWN is clear.
Table 12-35 Transmit Descriptor Field Descriptions
Word 0 Fields
Bit(s)
Field
63
OWN
62:59
-
58:48
Buffer1 Size (2K)
47:37
Buffer2 Size (2K)
36
TxERing
35
TxChain
34
TxSOF
33
TxEOF
32
TxEnCRCDes
31
–
30:20
TxFrmLen[10:0]
19:15
–
14:13
TxFrmType[1:0]
12
TxExDefer
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
Byte-Count Buffer 2
Figure 12-8 Transmit Descriptor Format
When set, indicates that the Descriptor is owned by the MAC. When reset, indicates that the
Descriptor is owned by the C790. MAC clears this bit either when it completes the frame
transmission or when the buffers that are allocated in the Descriptor are empty.
The Ownership bit of the first Descriptor of the frame should be set after all subsequent
Descriptors belonging to the same frame have been set. This avoids a possible race
condition between the MAC fetching a Descriptor and the driver setting an ownership bit.
Must be set to "0".
Indicates the size, in bytes, of the first data buffer. If this field is 0, the MAC ignores the
buffer and uses buffer2.
Indicates the size, in bytes, of the second data buffer. If TxChain is set (Address Chained),
the MAC ignores this buffer and fetches the next Descriptor.
Transmit End of Ring
When set, indicates that the Descriptor pointer has reached its final Descriptor. The MAC
returns to the base address of the list, creating a Descriptor ring.
Second Address Chained
When set, indicates that the second address in the Descriptor is the next Descriptor
address, rather than the second buffer address. If TxERing is set, TxChain is ignored.
Start of Frame
When set, indicates that the buffer contains the first byte of a frame.
End of Frame
When set, indicates that the buffer contains the last byte of a frame.
CRC Enable
When TxDesSelEn is set, this bit overrides the TxEnCRC bit in the TFCReg.
Reserved
Transmission Frame Length
Reserved
Transmit Frame Type
00 Ethernet
01 IEEE
10 VLAN I
11 VLAN II
Excessive Deferral
When set, indicates that the transmission was aborted because of an excessive deferral as
defined by the defer bit in the transmit frame configuration register. This bit is not valid for
12-40
Control Bits
Buffer Address 2
Description
Status Bits
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