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15.7 MCU Interface
Figure 15-5 shows the transactions for the TSEI MCU Interface. In particular, it shows a
read access followed by a write access.
SimWave 3.15-E
TB_TSEI.CPU_CLK
TB_TSEI.CS_n
TB_TSEI.RD_n
TB_TSEI.WR_n
TB_TSEI.WAIT_n
dc
12
TB_TSEI.AD
2
TB_TSEI.AD_1
TB_TSEI.MPLEX_n
TB_TSEI.ALE
TB_TSEI.RESET_n
15.7.1
Read Access
The read access starts by placing the address of the register to be read on the address bus
A[1:0]. The Chip Select signal is asserted at the same time. These values are sampled on
the following positive clock edge and the output data is prepared during the next clock cycle.
Here the RD_n signal is also asserted, enabling the output on the data bus AD[7:0]. The
correct time to sample the value from the data bus is on the next positive clock edge of the
CPU clock. At the next positive clock edge, the RD_n signal is deasserting, tri-stating the
output drivers for the data bus. CS_n is deasserted on the following clock edge.
15.7.2
Write Access
Similar to Read Access above, Write Access begins by asserting the CS_n signal. The
address of the value to be written is placed on the data bus at the same time. On the next
positive clock edge, the value to be written is placed on the data bus and the WR_n signal is
asserted simultaneously. The Wait signal is also asserted and remains asserted for one
clock cycle. The WR_n signal remains asserted for two clock cycles. The deassertion of the
CS_n signal ends the transfer on the following clock edge.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 15: Serial Port Interface
05
1
Figure 15-5 MCU Interface Signaling
15-11
Mon Dec 7 14:06:42 1998
dc
2
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