Fifo Operation - Toshiba TX79 Series User Manual

Tx system risc symmetric 2-way superscalar 64-bit cpu
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12.5.2

FIFO Operation

FIFOs are used internally to buffer frames before they are transmitted on the network or
before they are put to memory. The TxFIFO (1 KB) is deep enough to support the
retransmission of a frame if a collision occurs within the first 512 bit times of transmission.
The RxFIFO (1 KB) is deep enough to filter undersized and fragmented frames without
having to interrupt the host.
12.5.2.1 Threshold
Both the TxFIFO and RxFIFO have their own thresholds. The number is between 256 and 0.
But it is highly recommended to use a multiple of 16, such as 32, 64, 128 for the byte size.
DMA could take the burst transaction instead of the single transaction.
TxSOFTh and PBL are used to monitor the TxFIFO operation. TxSOFTh is used to start a
transmission after this number of data is written to the TxFIFO. PBL is used to monitor how
many free spaces are left in the TxFIFO. If there is no such free space, TxFrmReq will be
placed on hold. Therefore, there is no overflow in the TxFIFO.
In general, TxSOFTh should be more than 64 bytes, multiple of PBL and meet
(TxSOFTh + PBL) ≤ TxFIFO
(TxFIFO - PBL) > PBL
RxSOFTh and PBL are used to monitor the RxFIFO operation. RxSOFTh specifies when the
first DMA request is asserted after a frame is received. PBL is used to warn the MAC that
only this number of free spaces is left in the RxFIFO. For each frame, after reaching
RxSOFTh, subsequent DMA requests are governed by the PBL. This allows the first burst of
the frame to be different than the typical burst capability of the host. If there is not enough
data to be transferred, RxFrmReq will be placed on hold. This avoids underflowing in the
RxFIFO.
In general, the more RxSOFTh, the better. It should be more than 64 bytes, a multiple of
PBL and meet the following condition:
(RxFIFO - PBL) > PBL
12.5.2.2 Loopback
MAC supports two kinds of internal loop back operations for diagnostic purposes.
FIFO Level Loop Back
Data are written to the TxFIFO and transmitted to the RxFIFO internally. No data are sent
across the MII. The three threshold values are maintained in addition to the Tx and Rx FIFO
handshake signals. This loop back allows the host to perform a DMA in order to executed a
FIFO self-check. Status bits and event counters are not updated.
MII Level Loop Back
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
12-45

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