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8.5 PCI Core
8.5.1 Overview
This section describes the TX7901's PCI core with FIFOs. It covers the 66 MHz
Asynchronous Host Bridge and Satellite cores.
8.5.2 Features
The TX7901's PCI Host Bridge and Satellite core provide the following major features:
•
32-bit PCI bus path
•
32- or 64-bit G-Bus data path
•
PCI 2.1 compliant
•
Master operations and Target operations
•
Eight-location FIFO in each data path
•
Full Bandwidth Burst Mode
•
Memory Write and Invalidate support
•
Memory Read Multiple support
•
Dual Address Cycle support
•
Loadable Configuration Space
•
Fast Back-to-Back Target cycles support
•
Automatic or Manual retry for most efficient use of PCI bus
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
8-31
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