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8.2.3 PCI Master Writing to G-Bus Slave (Bridge Target Write)
The PGB performs posted writes for all memory and I/O write transactions to the
G-Bus. PCI configuration transactions to the PGB are not forwarded to the G-Bus.
Although PCI bursts may be of arbitrary length, burst transactions on the G-Bus can only
have "packet" sizes as shown in the table below. Because of this, a Bridge target write
strategy is implemented as described below.
GBTZ
000
001
Transactions on the G-Bus, whether for memory or I/O, can also be non-burst 32-bit or 64-
bit single data transactions.
8.2.3.1
Posted Write
The PGB breaks large PCI bursts of data into smaller bursts that fit into the PCI Bridge write
FIFO. The PGB write FIFO can hold a burst of size two quad-wards. The core provides the
word count of the current burst to the G-Bus. Any burst transaction that either comes in with
a size not conforming to the sizes of Table 8-2 or has some bytes disabled is broken down
into a minimum number of smaller size bursts that conform to the sizes in Table 8-2. Posted
writes from the PCI bus to the G-Bus can happen in parallel with posted writes from the G-
Bus to the PCI bus. Bursts transmitted onto the G-Bus have all Byte Enables active. When
the target is a 32-bit data target, the PGB drives the upper 32 data bits to zero. For such a
transaction, the PGB sets the upper four Byte Enable bits to ones. (One means "disabled".)
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
Table 8-2 G-Bus Burst Sizes
# of Quad-word
# of Transfers for
Equivalent
64-bit Device
1
2
# of Transfers for
32-bit Devices
2
4
8-9
4
8
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