Toshiba TX79 Series User Manual page 5

8.2.12 Reset................................................................................................................................... 8-16
8.2.13 Retry requests .................................................................................................................... 8-17
8.3 PGB M
EMORY
8.3.1 PCI Configuration Registers.............................................................................................. 8-18
8.3.2 PGB G-Bus Registers......................................................................................................... 8-20
8.4 R D
EGISTER UAL
8.4.1 pgbCSR[1] Dual Porting ................................................................................................... 8-30
8.4.2 p2gBase[3] Dual Porting .................................................................................................. 8-30
8.4.3 Protection Strategy ............................................................................................................ 8-30
8.5 PCI C ............................................................................................................................... 8-31
ORE
8.5.1 Overview ............................................................................................................................ 8-31
8.5.2 Features ............................................................................................................................. 8-31
8.6 A
RCHITECTURE
8.6.1 Major Internal Modules..................................................................................................... 8-32
8.6.2 I/O Signals for PCI Core ................................................................................................... 8-34
8.6.3 TRDY_TIMEOUT .............................................................................................................. 8-36
8.6.4 RETRY_TIMEOUT ............................................................................................................ 8-36
8.6.5 PCI Target Delayed Read Handling.................................................................................. 8-36
8.7 C
ONFIGURATION
8.7.1 PCI Vendor ID Register..................................................................................................... 8-37
8.7.2 PCI Device ID Register ..................................................................................................... 8-37
8.7.3 PCI Command Register ..................................................................................................... 8-37
8.7.4 PCI Status Register............................................................................................................ 8-38
8.7.5 Device Revision Identification Register............................................................................. 8-38
8.7.6 Class Code Register........................................................................................................... 8-39
8.7.7 Cache-Line Size Register ................................................................................................... 8-39
8.7.8 Master Latency Timer Register.......................................................................................... 8-40
8.7.9 Header Type....................................................................................................................... 8-40
8.7.10 Subsystem Vendor ID......................................................................................................... 8-40
8.7.11 Subsystem ID Register ....................................................................................................... 8-41
8.7.12 Interrupt Line Register....................................................................................................... 8-41
8.7.13 Interrupt Pin Register ........................................................................................................ 8-41
8.7.14 MIN_GNT Register ............................................................................................................ 8-42
8.7.15 MAX_LAT Register ............................................................................................................ 8-42
8.7.16 TRDY Timeout Value ......................................................................................................... 8-42
8.7.17 Retry Timeout Value .......................................................................................................... 8-43
CHAPTER 9. DMA CONTROLLER ................................................................................................. 9-1
9.1 M O
ODES OF PERATION
9.1.1 DMA Channel Priority......................................................................................................... 9-2
9.1.2 Source and Destination........................................................................................................ 9-3
9.1.3 Block Transfers .................................................................................................................... 9-3
9.1.4 Slice Transfers ..................................................................................................................... 9-4
9.1.5 C790 Cycle Stealing ............................................................................................................ 9-4
9.1.6 Chain Mode ......................................................................................................................... 9-6
9.1.7 Appending to The End of a Chain........................................................................................ 9-6
9.1.8 Bus Error ............................................................................................................................. 9-6
9.1.9 32-/64-bit G-Bus I/O............................................................................................................ 9-7
9.1.10 Memory Byte Alignment Support ......................................................................................... 9-7
9.1.11 Restarting a Disabled Channel............................................................................................ 9-8
9.1.12 Reprogramming an Active Channel..................................................................................... 9-8
9.1.13 Restrictions .......................................................................................................................... 9-8
9.2 R ................................................................................................................................ 9-9
EGISTERS
9.2.1 Channel Control Registers (CCR0 - CCR7) ...................................................................... 9-10
9.2.2 Channel Status Register (CSR0 - CSR7) ........................................................................... 9-13
TX7901 User's Manual (Rev. 6.30T - Nov, 2001)
Table Of Contents
M ............................................................................................................... 8-18
AP
-P ...................................................................................................... 8-30
ORTING
...................................................................................................................... 8-32
R D
EGISTER ESCRIPTIONS
............................................................................................................. 9-2
............................................................................ 8-37
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