Toshiba TX79 Series User Manual page 57

Tx system risc symmetric 2-way superscalar 64-bit cpu
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The following table is a register map of the individual modules. Please note that this table is
still under construction. See the tables in each relevant chapter for more information.
Name
NRPR3
Channel 3 Next Record Pointer Register
--
CCR4
CSR4
SAR4
DAR4
Channel 4 Destination Address Register
BCR4
NRPR4
Channel 4 Next Record Pointer Register
--
CCR5
CSR5
SAR5
DAR5
Channel 5 Destination Address Register
BCR5
NRPR5
Channel 5 Next Record Pointer Register
--
CCR6
CSR6
SAR6
DAR6
Channel 6 Destination Address Register
BCR6
NRPR6
Channel 6 Next Record Pointer Register
--
CCR7
CSR7
SAR7
DAR7
Channel 7 Destination Address Register
BCR7
NRPR7
Channel 7 Next Record Pointer Register
--
G–Bus Bridge / Chip Configuration / Interrupt Controller, Base Address 0x1E00_2000
SCR
BCR
BSR
BBAR
UIRA
LIRA
UROMA
LROMA
CGUPA0
CGLPA0
CGUPA1
CGLPA1
CGUPA2
CGLPA2
CGUPA3
CGLPA3
GCUIRA
GCLIRA
GCUMA0
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 4: Address Maps
Register Description
RESERVED
Channel 4 Control Register
Channel 4 Status Register
Channel 4 Source Address Register
Channel 4 Byte Count Register
RESERVED
Channel 5 Control Register
Channel 5 Status Register
Channel 5 Source Address Register
Channel 5 Byte Count Register
RESERVED
Channel 6 Control Register
Channel 6 Status Register
Channel 6 Source Address Register
Channel 6 Byte Count Register
RESERVED
Channel 7 Control Register
Channel 7 Status Register
Channel 7 Source Address Register
Channel 7 Byte Count Register
RESERVED
System Configuration Register
C790 Bus Control Register
C790 Bus Status Register
C790 Bus Bad Address Register
CG Upper Internal Register Address
CG Lower Internal Register Address
CG Upper ROM Address Register
CG Lower ROM Address Register
CG Upper PCI Address 0
CG Lower PCI Address 0
CG Upper PCI Address 1
CG Lower PCI Address 1
CG Upper PCI Address 2
CG Lower PCI Address 2
CG Upper PCI Address 3
CG Lower PCI Address 3
GC Upper Internal Register Address
GC Lower Internal Register Address
GC Upper MEM Address 0
Address
0x1E00_1350
0x1E00_1360 -0x1E00_13F0
0x1E00_1400
0x1E00_1410
0x1E00_1420
0x1E00_1430
0x1E00_1440
0x1E00_1450
0x1E00_1460 -0x1E00_14F0
0x1E00_1500
0x1E00_1510
0x1E00_1520
0x1E00_1530
0x1E00_1540
0x1E00_1550
0x1E00_1560 -0x1E00_15F0
0x1E00_1600
0x1E00_1610
0x1E00_1620
0x1E00_1630
0x1E00_1640
0x1E00_1650
0x1E00_1660 -0x1E00_16F0
0x1E00_1700
0x1E00_1710
0x1E00_1720
0x1E00_1730
0x1E00_1740
0x1E00_1750
0x1E00_1760 -0x1E00_1FF0
0x1E00_2000
0x1E00_2008
0x1E00_2010
0x1E00_2018
0x1E00_2020
0x1E00_2028
0x1E00_2030
0x1E00_2038
0x1E00_2040
0x1E00_2048
0x1E00_2050
0x1E00_2058
0x1E00_2060
0x1E00_2068
0x1E00_2070
0x1E00_2078
0x1E00_2080
0x1E00_2088
0x1E00_2090
4-4
R/W
Size(b)
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R
64
R/W
64
R/W
64
R
64
R
64
R
64
R
64
R
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R/W
64
R
64
R
64
R/W
64

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