Table 7-22 G-Bus Brokenm; Table 7-23 G-Bus Slave Latency - Toshiba TX79 Series User Manual

7.6.20 G- Bus Broken Master Latency Timer
The latency timer specifies the maximum period in which the master has to claim the G-bus
after the G-bus is granted. The counter is decremented at every B-Bus clock cycle. The
counter starts counting down when the arbiter asserts the grant signal. If the counter is down
to zero and the master device does not respond, an interrupt is signaled to the C790, and
the corresponding master status bit is set.
63
31
Bits
63:8
7:0 GBBMLT
7.6.21 G- Bus Slave Latency Timer
The slave latency timer specifies the maximum period in which the slave must acknowledge
the master. The counter is decremented at every G-Bus clock. The counter starts counting
down when the master asserts the STARTB signal. If the counter is down to zero and the
slave device does not respond, a G-Bus error is generated and the master generates an
interrupt signal to inform the C790.
63
31
Bits
63:16
15:0
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 7: C790 Bus/G-Bus Bridge
0
24
Table 7-22 G-Bus Broken Master Latency Timer
Field R/W
Reserved. Must be written as zeroes, and
– R/O
returns zeroes when read.
G-Bus Broken Master Latency Timer. Is
R/W
counted down by the G-Bus clock.
0
16
Table 7-23 G-Bus Slave Latency Timer
Field R/W
Reserved. Must be written as zeroes, and
– R/O
returns zeroes when read.
Latency Timer. Is counted down by the G-
GBSLT R/W
Bus clock.
0
32
8 7
Description
0
32
16 15
GBSLT
16
Description
7-18
32
0
GBBMLT
8
Initial Value
0
0xFF
32
0
Initial Value
0
0xFFFF