Table of Contents
Advertisement
Name of Signal
MAC1_MDC
MAC1_MDIO
MAC1_HwFDupSel
Timer/Counter Interface
TIMOUT1
TIMIN1
TIMOUT2
TIMIN2
Serial Peripheral Interface
SPI_MISO
SPI_MOSI
SPI_Clk
SPI_Port0B
SPI_Port1B
SPI_Port2B
SPI_Port3B
SPI_Port4B
SPI_Port5B
PCI0 Interface
PCI0_AD[31:0]
PCI0_CBEB[3:0]
PCI0_PAR
PCI0_FRAMEB
PCI0_TRDYB
PCI0_IRDYB
PCI0_STOPB
PCI0_DEVSELB
PCI0_CLK
PCI0_PERRB
PCI0_IDSEL
PCI0_SERRB
PCI0_REQB
PCI0_GNTB
PCI0_GNT0B
PCI0_REQ1B
PCI0_GNT1B
PCI0_REQ2B
PCI0_GNT2B
PCI1_REQ1B_PCI0_REQ3B
PCI1_REQ2B_PCI0_REQ4B
PCI0_RSTB
PCI1 Interface
PCI1_AD[31:0]
PCI1_CBEB[3:0]
PCI1_PAR
PCI1_FRAMEB
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 17: Pins
I/O
O
MII Management Clock
I/O
MII Management Data Input/Output
I
Full Duplex Select
O
Timer 1 Output
I
External Clock Input for Timer 1
O
Timer 2 Output
I
External Clock Input for Timer 2
I
Serial Data Input
O
Serial Data Output
O
SPI Data Clock
O
SPI Chip select for SPI device 0
O
SPI Chip select for SPI device 1
O
SPI Chip select for SPI device 2
O
SPI Chip select for SPI device 3
O
SPI Chip select for SPI device 4
O
SPI Chip select for SPI device 5
I/O
The 64 Bit Address and Data Buses are multiplexed on the same PCI pins.
I/O
Command and Byte Enable
I/O
Parity for PCI_AD[31:0] and PCI_CBE[3:0]B Even Parity
I/O
Indicates beginning and duration of a transaction.
I/O
Target Ready
I/O
Initiator Ready
PCI_STOPB Indicates that the current Target is requesting Initiator to stop the
I/O
current transaction.
Device select; it indicates that the current driving device has decoded its address
I/O
as the target of the current access.
I
PCI Clock Input
Data Parity Error
I/O
Reporting parity error on all transactions except Special Cycle command.
Initialization Device Select
I
It is used as a chip select during configuration read/write transaction on PCI bus.
System Error
Reporting errors for all the address parity errors and data parity error on Special
O
Cycle commands, and may optionally be used on any other non-parity or system
errors.
O
PCI0 request signal to PCI arbiter
I
PCI0 bus Grant form PCI arbiter
I
PCI0 bus Grant 0B
O
PCI0 Request 1B
I
PCI0 bus Grant 1B
O
PCI0 Request 2B
I
PCI0 bus grant 2B
O
PCI1 Request 1B Multiplex with PCI10 Request 3B
O
PCI1 Request 2B Multiplex with PCI10 Request 4B
I
PCI0 Reset signal
I/O
The 64 Bit Address and Data Buses are multiplexed on the same PCI pins.
I/O
Command and Byte Enable
I/O
Parity for PCI_AD[31:0] and PCI_CBEB[3:0] Even Parity
I/O
Indicates beginning and duration of a transaction.
17-3
Function
Advertisement
Table of Contents
