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9.2.4
Destination Address Register (DAR0 - DAR7)
These eight registers contain the destination address of the DMA operation in progress for
each of the eight DMA channels.
63
31
Table 9-6 Destination Address Register Field Definitions
Bit(s)
Field
63:32
–
31:0
DA
9.2.5
Byte Count Register (BCR0 – BCR7)
These eight registers contain the byte counts of the DMA operation in progress for each of
the eight DMA Channels.
63
31
0
8
Table 9-7 Current Byte Count Register Field Definitions
Bit(s)
Field
63:24
–
23:0
BC
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 9: DMA Controller
0
32
DA[31:0]
32
R/W
Default
R/O
0
Reserved
Destination Address - CDA[31:0]
For each DMA write cycle to the destination device, the
destination address is updated depending on the Destination
Device Counting Mode (DCM). If the channel is programmed
R/W
0
in the Chain Mode (CHN=1), the destination address is loaded
from the address pointed to by the Next Record Pointer
Register when a whole block of data has been completely
transferred.
0
32
24 23
R/W
Default
R/O
0
Reserved
Byte Count
For each DMA write cycle performed, the byte count is
decremented. If the channel is programmed in the Chain Mode
R/W
0
(CHN=1), the byte count register is loaded from the address
pointed to by the Next Record Pointer Register when a whole
block of data has been completely transferred.
Description
BC[23:0]
24
Description
9-15
32
0
32
0
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