Explanation Of Operation; Program Counter (Pc); Stack Register (Stack); Program Memory (Rom) - Toshiba TC9314F Manual

Explanation of Operation

CPU
CPU is composed of program counter, stack register, ALU, program memory, data memory, G-register, carry
F/F and judging circuit.

1. Program Counter (PC)

Program Counter is a block to designate the address of program memory (ROM), and is composed of 13
bits binary up counter. This is cleared by system reset, and the program starts from zero address.
Usually, it's increment is made one by one everytime the one instruction is executed, but when JUMP
instruction or CAL instruction is executed, the address designated at operand part of that instruction is
loaded.
Further, when the instruction (SLT1, TMT, SKP, RNS instructions, etc.) having skip function is executed,
two increments of program counter is made if the result is the condition to be skipped, and the succeeding
instruction is skipped.

2. Stack Register (STACK)

This is a register composed of 4
obtained by adding 1 to the content of program counter, namely return address, is housed. The content of
stack register is loaded on the program counter by the execution of return instruction. (RN, RNS
instructions)
This stack level is 4 level, and nesting is 4 level.
3. ALU
ALU has binary 4 bits parallel addition and subtraction, logical operation, comparison and plural bit
judge functions.
This CPU has no accumulator, and all operations directly treat the contents of data memory.

4. Program Memory (ROM)

Program memory is composed of 16 bit
Program memory has no concept of page or field, so JUMP instruction and CAL instruction can be freely
used among 6144 steps.
Further, it is possible to use optional address of program memory as data area, and its content, 16 bits,
can be loaded to the data register by executing DAL instruction.
Note 6: Provide the data area at the address outside the program loop in the program memory.
Note 7: In DAL instruction, the address of program memory can be designated as the data area becomes 1024
steps of 0000H~03FFH.
13 bits during the execution of subroutine call instruction, the value
6144 steps and is the address of 0000H~17FFH.
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TC9314F
2003-07-03