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Table 9-1 shows the types of transfer that can be performed in block mode.
9.1.4 Slice Transfers
The slice mode is designed for I/O to memory and memory to I/O transfers. When the I/O
device needs more than one slice of data to transfer to/from memory, the I/O device sends a
request to the DMAC to perform a slice transfer.
In the slice mode, each hardware or software DMA request sends a request to the DMAC to
transfer one slice of data. The size of the slice (SLS[2:0]) of data is selected in the
corresponding DMA channel control register (one of CCR0 – CCR7).
When slice mode DMA channel access is granted, the DMAC arbitrates for the source bus
to become a bus master. When the DMAC is granted the source bus, it transfers only one
slice of data from the source device to the FIFO. The DMAC now arbitrates for the
destination bus, and when the bus is granted, it transfers the slice of data from the FIFO to
the destination device. Once the slice of data is transferred, the DMAC is ready to serve
other DMA channels. Essentially, in the slice mode, the entire DMA transfer is broken down
into a number of slice transfers. At the end of the very last slice transfer, the DMAC
generates an interrupt to the C790.
The target memory address should be quad-word aligned for efficient data transfer.
Otherwise, the number of read/write cycles required for the DMA transfer would increase by
one per slice transfer. For example, if the whole DMA transfer requires 300 slice transfers
from or to the C790 bus memory, the DMA transfer will increase by 300 C790 bus clock
cycles.
9.1.5
C790 Cycle Stealing
If cycle stealing is enabled, the C790 is allowed to steal some cycles from the C790 bus in
the middle of a DMA block or slice transfer. Otherwise, during the DMA block or slice
transfer, the C790 is idle. This feature is for data synchronization between the DMAC and
the C790.
When C790 cycle stealing is disabled, the C790 cannot use any system
resources until the DMA transfer is complete.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 9: DMA Controller
Table 9-1 Block and Slice Transfer Types
Block Mode
• Memory to I/O
• I/O to Memory
• Memory to Memory
9-4
Slice Mode
• Memory to I/O
• I/O to Memory
• Memory to Memory
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