Receive Buffer Register (Rbr0, Rbr1) - Toshiba TX79 Series User Manual

14.4.2

Receive Buffer Register (RBR0, RBR1)

This register is updated from the RX Shift Register at the end of a receive sequence. If the
FIFOs are disabled, this register is undefined after reset. If the FIFOs are enabled, this
register will return "0" after reset if the RX FIFO is empty. This register receives data from
the FIFOs when the FIFO mode is enabled.
14.4.3 Transmit Holding Registers (THR0, THR1)
Data are held in this register until transferred to the TX Shift Register when in a non-FIFO
mode. Data are sent to FIFOs when the FIFO mode is enabled.
14.4.4 Line Control Registers (LCR0, LCR1)
Table 14-4 lists the fields of the Line Control Registers. This register specifies line control
parameters and contains the DLAB bit which makes the Divisor Latch addresses accessible.
Table 14-4 Line Control Register Field Descriptions
Bit
0
1
2
3
4
5
6
7
After reset, bits 0 through 7 are all zero.
14.4.4.1 WLS0, 1 – Word Length Select
Transmitted and Received character size is defined as follows:
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 14: UARTS WITH FIFOS
Read/
Write
WLS0 Word Length Select
WLS1 Word Length Select
STB Number of Stop Bits
PEN Parity Enabled
EPS Even Parity Select
SP Stick Parity
SB Set Break
Divisor Latch Access Bit. Controls access to alternate
DLAB
registers at Addresses 0 and 1
Table 14-5 Transmit and Receive Character Size
WLS1 WLS0
0
0
1
1
Comments
Character Size
0 5-bit
1 6-bit
0 7-bit
1 8-bit
14-6