Interrupt Enable Registers (Ier0, Ier1) - Toshiba TX79 Series User Manual

14.4.8

Interrupt Enable Registers (IER0, IER1)

Table 14-11 details the functionality of the Interrupt Enable Register bit fields.
Field
Bit(s)
Name
7:4 – Reserved
Enable Modem Status Interrupt. When set ("1"), an interrupt is generated if D0, D1, D2, or D3 of the
3 EDSSI
Modem Status Register have been set.
Enable RX Status Interrupt. When set ("1"), an interrupt is generated if D1, D2, D3 or D4 of the Line
2 ELSI
Status Register have been set.
Enable TX Holding Register Empty Interrupt. When set ("1"), an interrupt is generated if either
1 ETBEI
THRE=1 or the TX Holding Register is empty.
0 ERBFI Enable RX Buffer Register. When set ("1"), an interrupt is generated if the RX Buffer contains data.
Note: After reset, bits 0 through 7 are all "0".
14.4.9 Modem Control Registers (MCR0, MCR1)
After reset, bits 0 through 7 are all zero.
14.4.9.1 LOOP
When set ("1"), the following conditions are implemented:
1. SOUT is forced to "1."
2. SIN is disconnected from the RX Shift Register input.
3. RX Shift Register input is connected to TX Shift Register output.
4. The Modem status signals (CTS*, DSR*, DCD*, and RI*) are disconnected.
5. The Modem control signals are connected to the modem status inputs (RTS* to CTS*,
DTR* to DSR*, OUT1* to RI*, OUT2* to DCD.)
When clear ("0"), the Modem control/status signals and SIN/SOUT are as normal.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 14: UARTS WITH FIFOS
Table 14-11 Fields of Interrupt Enable Registers
Table 14-12 Modem Control Register Fields
Bit(s) Write
7:5 X
4 Loop
3 OUT2
2 OUT1
1 RTS
0 DTR
Description
Read Comment
0
Loop Loop-back mode
OUT2 Control Signal
OUT1 Control Signal
RTS Control Signal
DTR Control Signal
14-13