Divisor Latch Ls And Ms Registers (Dll, Dlm) - Toshiba TX79 Series User Manual

14.4.13 Divisor Latch LS and MS Registers (DLL, DLM)

The table below shows the divisor needed to generate a prescaler output of approximately 8
MHz. The effective Clock Enable generated is 16x the required baud rate.
Table 14-14 Prescaler output and divide values for various CPU & G-Bus Clocks
RefClk
(MHz)
133
100
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 14: UARTS WITH FIFOS
G Bus Clock
(MHz)
66.6
50.0
66 33.3
Table 14-15 Clock Frequency and Percent Error
Pre-scaled
Clock
Baud Rate
50
75
110
135
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
Divide Prescaler Output
Value
8
6
4
8.3333 MHz
Divisor
Error
for 16x
%
clock
10417 -0.00320
6944 0.00640
4735 -0.00320
3872 0.00947
3472 0.00640
1736 0.00640
868 0.00640
434 0.00640
289 0.12175
260 0.16026
217 0.00640
145 -0.22350
109 -0.45234
72 0.46939
54 0.46939
27 0.46939
14 -3.11880
9 3.33995
4 1.72526
2 1.72526
14-16
(MHz)
8.333
8.333
8.333