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Bit(s)
Field
7:5
PBL
4
BAR
3
CntRst
2
RxRst
1
TxRst
0
SwRst
12.3.1.2 Transmit Frame Configuration Register (TFCReg)
The Transmit Frame Configuration Register defines the transmission rules for the MAC.
These can be changed to accommodate different options. Upon the completion of reset, this
register's default value is 0x2008_0100.
31
30
0
TxFIFOSize
1
3
15
14
13
Hw
Dup
F
Loop
Self
Dup
En
En
1
1
1
Bit(s)
Field
31
–
TxFifoSize
30:28
[2:0]
27
TxFlwCnt
26
TxSQEEn
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
R/W
Programmable Burst Length (011)
Indicates the maximum number of 8-byte values to be transferred in one DMA
transaction.
X00 2 (16 bytes)
X01 4 (32 bytes)
R/W
X10 8 (64 bytes)
X11 16 (128 bytes)
It is also a kind of count threshold, and has different definitions in the TxFIFO and the
RxFIFO. This threshold guarantees that a PBL space of at least 8 bytes is either free
to write to the TxFIFO or to contain data to read from the Rx_FIFO.
Bus Arbitration
Selects the internal bus arbitration between the receive and transmit processes. When
R/W
set, a round-robin arbitration scheme is applied resulting in equal sharing between
processes. When reset, the receive process has priority over the transmit process. (0)
Counter Reset. This bit provides counter reset only. It will be kept active for at least 40
R/W
gbsBusClk periods. This bit is self-clearing. (0)
Receive Port Reset. This bit provides Receive Port reset only. This bit is self-clearing.
R/W
(0)
Transmit Port Reset. This bit provides Transmit Port reset only. This bit is self-
RW
clearing. (0)
Software Reset. Reset is immediate and it is equivalent to resetting the counters, the
transmitters, the receivers, and the MII management block. It does not affect registers,
RW
including interrupt status or diagnostic registers. This bit is self-clearing. (0)
Note: The Busy bit in the MII control register must be 0 before this bit is set.
28
27
26
TxSQE
TxFlw
Cnt
En
1
1
12
11
10
9
TxEn
Loop
TxEn
TxEn
CRC
Sel
CRC
Pad
Sel
1
1
1
1
Table 12-8 TFCReg Register Field Descriptions
R/W
R/O
Reserved
TxFIFO Size Select (010)
010
R/W
000, 001, 011-111 : Reserved. Try to avoid changing these values.
Transmit Flow Control
R/W
This bit must remain cleared. Do not try to set this bit.
SQE Test Enable (0)
R/W
When TxSQE is 0, the transmitter does not report the status of the SQE test performed by
Description
25
24
23
0
2
8
7
6
5
Tx
TxRetry
TxEn
BOff
Halt
Sel
Sel
1
2
1
Description
: Size = 1 KB (128 x 64 bits)
12-9
TxSOFTh[7:0]
8
4
3
2
1
TxPreAm
TxAb
Tx
Defer
Sel
Start
1
2
1
16
0
Tx
Ena-
ble
1
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