Toshiba TX79 Series User Manual page 249

Word 0 Fields
Bit(s) Field
11 TxDefer
10 TxSCol
9 TxMCol
8 TxExCol
7 TxLCol
6 TxLCar
5 SQE
4 TxUndf
3 –
2 TxNoBuf
1 TxPStop
0 TxGOOD
Word 1 Fields
Bit(s) Field
63:32 Buffer Address 1
31:0 Buffer Address 2
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
full-duplex.
Deferred
When set, indicates the frame transmission was delayed because of a deferral. This bit is
set when a frame is transmitted with a collision and the standard backoff is selected in the
configuration register. This bit is not valid while the port is configured for full-duplex.
Single Collision
When set, indicates that the frame being transmitted collided only once and was then
transmitted successfully on the Ethernet.
Multiple Collisions
When set, indicates that the frame being transmitted collided more than once and was then
transmitted successfully on the Ethernet.
Collision Error
When set, indicates that the frame transmission was aborted because of too many
collisions. The number of collision retries allowed is specified in the transmit frame
configuration register.
Late Collision
When set, indicates that a transmission is aborted due to a collision occurring later than 512
bit times.
Loss of Carrier
When set, indicates the CRS input is Low during the transmission of a frame.
Signal Quality Error Missed
When set, indicates that the SQE test on the macxCOL signal line is not detected at the end
of a transmission.
Transmit Underflow
When set, indicates that the TxFIFO had an underflow condition during the frame
transmission. The transmission process is suspended.
Reserved
Transmit Buffer Unavailable
When set, indicates that the next Descriptor in the transmit list is owned by the host and
cannot be acquired by the MAC. The transmission process is suspended.
Transmit Process Stopped
When set, indicates that the transmit process has stopped.
Good Frame
When set, indicates that a frame transmission was completed without error. This bit will be
set regardless of the state of SQE, TxSCol, TxMCol and TxDefer. This bit will not be set
when TxLCol, TxExDefer, TxExCol or TxUndf
This address points to buffer 1 locations. This address must be 8-byte aligned.
This address points to buffer 2 locations. This address must be 8-byte aligned.
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Description
Description